Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10559569-B2
Application number	US-201715700615-A
Country	US
Kind code	B2
Filing date	Sep 11, 2017
Priority date	Dec 21, 2016
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a transistor in a semiconductor substrate;
forming a capacitor including a hydrogen-containing top electrode, the hydrogen-containing top electrode being positioned over the transistor to overlap with the transistor; and
performing an annealing process for a hydrogen passivation after the capacitor is formed.

2. The method of claim 1 , wherein the forming of the capacitor includes:
forming a bottom electrode;
forming a dielectric layer over the bottom electrode;
forming a top electrode layer over the dielectric layer;
performing a plasma doping process for doping the top electrode layer with hydrogen; and
etching the top electrode layer.

3. The method of claim 2 , wherein the top electrode layer includes a silicon germanium layer.

4. The method of claim 2 , wherein the bottom electrode has a pillar shape or a cylindrical shape.

5. The method of claim 1 , wherein the forming of the capacitor includes:
forming a bottom electrode;
forming a dielectric layer over the bottom electrode;
forming a first top electrode layer over the dielectric layer;
forming a second top electrode layer over the first top electrode layer;
performing a hydrogen plasma doping process onto the second top electrode layer to form a hydrogen-doped second top electrode layer;
forming a third top electrode layer over the hydrogen-doped second top electrode layer; and
etching the third top electrode layer, the hydrogen-doped second top electrode layer, and the first top electrode layer to form the hydrogen-containing top electrode.

6. The method of claim 5 , wherein the second top electrode layer includes a silicon germanium layer.

7. The method of claim 5 , wherein the first top electrode layer and the third top electrode layer include a metal-containing layer.

8. The method of claim 5 , wherein the bottom electrode has a pillar shape or a cylindrical shape.

9. The method of claim 1 , wherein the forming of the transistor includes:
forming a gate trench in the semiconductor substrate;
forming a gate dielectric layer in the gate trench; and
forming a gate electrode filling the gate trench over the gate dielectric layer.

10. The method of claim 1 , further comprising:
forming a bit line after the forming of the transistor before the forming of the capacitor.

11. The method of claim 1 , wherein the annealing process is performed in an atmosphere of a hydrogen-containing gas.

12. A method for fabricating a semiconductor device, comprising:
preparing a semiconductor substrate including a cell region and a peripheral circuit region;
forming a first transistor in the semiconductor substrate of the cell region;
forming a second transistor in the semiconductor substrate of the peripheral circuit region;
forming a capacitor including a hydrogen-containing top electrode, the hydrogen-containing top electrode being positioned over the first transistor to overlap with the first transistor; and
performing an annealing process for hydrogen passivation after the capacitor is formed.

13. The method of claim 12 , wherein the forming of the capacitor includes:
forming a bottom electrode;
forming a dielectric layer over the bottom electrode;
forming a top electrode layer over the dielectric layer;
performing a plasma doping process for doping the top electrode layer with hydrogen; and
etching the top electrode layer to form the hydrogen-containing top electrode disposed in the cell region.

14. The method of claim 13 , wherein the top electrode layer includes a silicon germanium layer.

15. The method of claim 12 , wherein the forming of the capacitor includes:
forming a bottom electrode;
forming a dielectric layer over the bottom electrode;
forming a first top electrode layer over the dielectric layer;
forming a second top electrode layer over the first top electrode layer;
performing a hydrogen plasma doping process onto the second top electrode layer to form a hydrogen-dope second top electrode layer;
forming a third top electrode layer over the hydrogen-doped second top electrode layer; and
etching the third top electrode layer, the hydrogen-doped second top electrode layer, and the first top electrode layer to form the hydrogen-containing top electrode disposed in the cell region.

16. The method of claim 15 , wherein the second top electrode layer includes a silicon germanium layer.

17. The method of claim 15 , wherein the first top electrode layer and the third top electrode layer include a metal-containing layer.

18. The method of claim 12 , wherein the forming of the first transistor includes:
forming a gate trench in the semiconductor substrate;
forming a gate dielectric layer in the gate trench; and
forming a gate electrode filling the gate trench over the gate dielectric layer.

19. The method of claim 12 , further comprising:
forming a bit line after the forming of the first transistor before the forming of the capacitor.

20. The method of claim 12 , wherein the annealing process is performed in an atmosphere of a hydrogen-containing gas.

Assignees

• Sk Hynix Inc

Inventors

• Jang Il-Sik
• Park Ji-Hwan
• Lee Mi-Ri
• Jeon Bong-Seok
• Joung Yong-Soo
• Hwang Sun-Hwan

Classifications

• H10P32/1204

  from a plasma phase · CPC title

• H10P95/94 Primary

  Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title