Methods, apparatus and system for a passthrough-based architecture

Patent metadata

Field	Value
Publication number	US-10559503-B2
Application number	US-201715728445-A
Country	US
Kind code	B2
Filing date	Oct 9, 2017
Priority date	Mar 11, 2016
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

First claim

What is claimed is:

1. A finFET device, comprising:
a first gate structure and a second gate structure on a semiconductor substrate;
a first active area contacting a first end of said first gate structure and contacting a first end of said second gate structure;
a second active area contacting a second end of said first gate structure and contacting a second end of said second gate structure; and
a self-aligned trench silicide (TS) structure configured to operatively couple said first active area to said second active area, wherein said TS structure is flush in height with said first gate structure and said second gate structure.

2. The finFET device of claim 1 , wherein said self-aligned TS structure is a borderless pass-through structure that provides a pass-through route between said first and second active areas.

3. The finFET device of claim 1 , further comprising a first local interconnect (CB) structure above at least one of said gate structures, wherein said CB structure is formed offset relative to said gate structure in a manner such that said CB structure does not contact the TS structure.

4. The finFET device of claim 3 , wherein CB structure is a self-aligned via defined in one direction by the borders of an M 0 metal formation.

5. The finFET device of claim 1 , wherein said first active area, said second active area and said TS structure each are defined by at least one of a plurality of cut masks.

6. The finFET device of claim 1 , further comprising a second local interconnect (CA) structure, wherein said CA structure is formed to make contact with said TS structure and said first active area.

7. The finFET device of claim 1 , wherein said first active area is a PMOS region and wherein said second active area is an NMOS region.

8. The finFET device of claim 1 , further comprising a first local interconnect (CB) structure above at least one of said gate structures, wherein said CB structure is formed offset relative to said gate structure in a manner such that said CB structure does not contact the TS structure; and
a second local interconnect (CA) structure, wherein said CA structure is formed to make contact with said TS structure and said first active area;
wherein a top of said CB structure and a top of said CA structure are coplanar.

9. The FinFET device of claim 8 , further comprising a metallization formation (M 0 ), wherein a top of said M 0 formation is coplanar with said top of said CB structure and said top of said CA structure.

Assignees

• Globalfoundries Inc

Inventors

• Bouche Guillaume
• Neogi Tuhin Guha
• Wei Andy Chi-Hung
• Zeng Jia
• Kye Jongwook
• Stephens Jason Eugene
• Lin Irene Yuh-Ling
• Raghunathan Sudharshanan
• Yuan Lei

Classifications

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• H10W20/0698

  Local interconnections · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H01L21/823821

  Electricity · mapped topic