Selective germanium P-contact metalization through trench

Patent metadata

Field	Value
Publication number	US-10553680-B2
Application number	US-201916402739-A
Country	US
Kind code	B2
Filing date	May 3, 2019
Priority date	Dec 21, 2010
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a fin comprising one or both of silicon and germanium;
a first gate structure on top and sidewalls of a first portion of the fin;
a p-type source or drain region to one side of the first gate structure;
a second gate structure on top and sidewalls of a second portion of the fin;
an n-type source or drain region to one side of the second gate structure;
a germanium layer on the p-type source or drain region, the germanium layer comprising a germanium concentration in excess of 50 atomic %;
a first contact structure on the germanium layer; and
a second contact structure on the n-type source or drain region.

2. The integrated circuit of claim 1 , further comprising first spacers for the first gate structure and second spacers for the second gate structure, the first spacers and second spacers arranged in opposing fashion about the first gate and second gate respectively so that at least part of the corresponding gate structure is between the first spacers and the second spacers.

3. The integrated circuit of claim 2 , wherein the fin includes a first recess and a second recess that extends under a corresponding one of the first and second spacers, and wherein at least one of the source regions is at least partially within the first recess and at least one of the drain regions is at least partially within the second recess.

4. The integrated circuit of claim 1 , wherein the p-type source or drain region and the n-type source or drain region comprise silicon or silicon and germanium.

5. The integrated circuit of claim 1 , wherein:
the first contact structure includes a germanide and a first body of metal; and
the second contact structure includes a silicide and a second body of metal.

6. The integrated circuit of claim 1 , wherein an overall thickness of the p-type and n-type source region is the distance between a bottom of the first contact structure and a bottom of the source region, and is in the range of 50 to 500 nm, and wherein the overall thickness of the p-type and n-type drain region is the distance between a bottom of the second contact structure and a bottom of the drain region, and is in the range of 50 to 500 nm.

7. The integrated circuit of claim 1 , wherein the first gate structure and the second gate structure include a dielectric material that comprises hafnium.

8. The integrated circuit of claim 1 , wherein the germanium layer further comprises a p-type dopant.

9. The integrated circuit of claim 1 , wherein the germanium concentration is over 90%.

10. The integrated circuit of claim 1 , wherein the germanium concentration is over 98%.

11. An integrated circuit, comprising:
a fin comprising one or both of silicon and germanium;
a first gate structure comprising a first gate electrode and a first gate dielectric, the first gate dielectric on a top and on sidewalls of a first portion of the fin, the first gate dielectric between the first gate electrode and the fin;
a p-type source or drain region to one side of the first gate structure;
a second gate structure comprising a second gate electrode and a second gate dielectric, the second gate dielectric on a top and on sidewalls of a second portion of the fin, the second gate dielectric between the second gate electrode and the fin;
an n-type source or drain region to one side of the second gate structure;
a germanium layer on the p-type source or drain region, the germanium layer comprising a germanium concentration in excess of 50 atomic %;
a first contact structure on the germanium layer; and
a second contact structure on the n-type source or drain region.

12. The integrated circuit of claim 11 , wherein at least one of the first gate dielectric and the second gate dielectric comprises hafnium.

13. The integrated circuit of claim 11 , wherein at least one of the first gate electrode and the second gate electrode comprises silicon.

14. The integrated circuit of claim 11 , wherein the p-type source or drain region and the n-type source or drain region comprise silicon or silicon and germanium.

15. The integrated circuit of claim 11 , wherein the first and second contact structures each include a layer of titanium on the corresponding source or drain region, a layer of titanium nitride on the layer of titanium, and a layer of tungsten on the layer of titanium nitride.

16. The integrated circuit of claim 11 , wherein an overall thickness of the p-type and n-type source region is the distance between a bottom of the first contact structure and a bottom of the source region, and is in the range of 50 to 500 nm.

17. The integrated circuit of claim 11 , wherein the overall thickness of the p-type and n-type drain region is the distance between a bottom of the second contact structure and a bottom of the drain region, and is in the range of 50 to 500 nm.

18. The integrated circuit of claim 11 , wherein the germanium layer further comprises a p-type dopant.

19. The integrated circuit of claim 11 , wherein the germanium concentration is over 90%.

20. The integrated circuit of claim 11 , wherein the germanium concentration is over 98%.

Assignees

• Intel Corp

Inventors

• Glass Glenn A
• Murthy Anand S
• Ghani Tahir

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/0111 Primary

  to Group IV semiconductors · CPC title