Systems and methods for semiconductor packages using photoimageable layers

Patent metadata

Field	Value
Publication number	US-10553453-B2
Application number	US-201616317789-A
Country	US
Kind code	B2
Filing date	Jul 14, 2016
Priority date	Jul 14, 2016
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

First claim

The invention claimed is:

1. A semiconductor package, comprising:
a carrier;
a first metal layer on at least one face of the carrier;
a first photoimagable layer on the first metal layer;
a second metal layer on the first photoimagable layer;
at least one first pad at least partially disposed over a first dry film resist layer and a patterned first photoimagable layer;
a patterned second photoimagable layer at least partially disposed over the at least one first pad and the patterned first photoimagable layer;
a second metal layer at least partially disposed over the patterned second photoimagable layer;
at least one second pad at least partially disposed over the patterned second photoimagable layers; and
a first photoresist layer at least partially disposed over the at least one first pad and the second patterned photoimagable layer.

2. The semiconductor package of claim 1 , wherein the first metal layer comprises one or more of copper or tin.

3. The semiconductor package of claim 1 , wherein the first metal layer further comprises a treated first metal layer, the treated metal layer further comprising a copper roughening treated surface of the first metal layer.

4. The semiconductor package of claim 1 , wherein the first metal layer further comprises a treated first metal layer, the treated metal layer further comprising an adhesion promoting treated surface of the first metal layer.

5. The semiconductor package of claim 1 , wherein the second metal layer further comprises a sputter seed formed second metal layer.

6. The semiconductor package of claim 1 , wherein the sputter seed formed second metal layer further comprises one or more of a titanium or a copper seed layer formed second metal layer.

7. The semiconductor package of claim 1 , further comprising one or more of a third metal layer at least partially disposed over the patterned second photoimagable layer and a second dry film resist layer at least partially disposed over the patterned second photoimagable layer.

8. The semiconductor package of claim 1 , wherein the second metal layer further comprises an electrodeless plated second metal layer.

9. The semiconductor package of claim 1 , wherein the at least one first pad further comprises an electrolytic plated first pad.

10. A method to form a semiconductor package, the method comprising:
providing a carrier;
forming a first metal layer on at least one face of the carrier;
forming a first photoimagable layer on the first metal layer;
forming at least one first pad at least partially disposed over the first photoimagable layer to produce a first structure;
forming a second photoimagable layer at least partially disposed over the at least one first pad and the first photoimagable layer;
forming at least one second pad at least partially disposed over the second photoimagable layer;
forming a first photoresist layer at least partially disposed over the at least one first pad and the second photoimagable layer to produce a second structure; and
removing, from the carrier, the second structure comprising the first photoresist layer.

11. The method of claim 10 , wherein the processing the first metal layer to treat a surface of the first metal layer further comprises a copper roughening treatment of the first metal layer.

12. The method of claim 11 , wherein the processing the first metal layer to treat a surface of the first metal layer further comprises an adhesion promoting treatment of the first metal layer.

13. The method of claim 10 , further comprising processing the first photoimagable layer to pattern the first photoimagable layer.

14. The method of claim 13 , further comprising one or more of forming a second metal layer at least partially disposed over the patterned first photoimagable layer, forming a first dry film resist layer at least partially disposed over the patterned first photoimagable layer, or processing the first dry film resist layer to pattern the first dry film resist layer.

15. The method of claim 14 , wherein the forming the second metal layer at least partially disposed over the patterned first photoimagable layer further comprises electrodeless plating the second metal layer.

16. The method of claim 14 , wherein the forming the second metal layer at least partially disposed over the patterned first photoimagable layer further comprises sputter seed formation of the second metal layer.

17. The method of claim 10 , further comprising a copper roughening treatment of a surface of the at least one first pad.

18. The method of claim 10 , wherein the method further comprises processing the second photoimagable layer to pattern the second photoimagable layer.

19. The method of claim 18 , wherein the method further comprises one or more of forming a third metal layer on the patterned second photoimagable layer, forming a second dry film resist layer on the patterned second photoimagable layer, or processing the second dry film resist layer to pattern the second dry film resist layer.

20. The method of claim 10 , wherein the forming at least one first pad at least partially disposed over the first photoimagable layer to produce a first structure further comprises electrolytic plating the at least one first pad metal layer.

Assignees

• Intel Corp

Inventors

• Chavali Sri Chaitra
• Alur Siddharth K
• Schuckman Amanda E
• Alur Amruthavalli Palla
• Salama Islam A
• Deng Yikang
• Darmawikarta Kristof

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title