Analog-digital converter having multiple feedback, and communication device including the analog-digital converter

Patent metadata

Field	Value
Publication number	US-10547322-B2
Application number	US-201816186761-A
Country	US
Kind code	B2
Filing date	Nov 12, 2018
Priority date	Jan 2, 2018
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

An analog-digital converter has multiple feedback, and includes: a capacitor digital-analog converter including a plurality of switches driven by a digital code, and a plurality of capacitors respectively connected to the plurality of switches, wherein the capacitor digital-analog converter is configured to generate a residue voltage based on an analog input voltage and a voltage corresponding to the digital code; first and second feedback capacitors each storing the residue voltage; an integrator configured to generate an integral signal by integrating the residue voltage; first and second comparators respectively configured to generate first and second comparison signals from the integral signal; and a digital logic circuitry configured to receive the first and second comparison signals, and generate a digital output signal from the first and second comparison signals, the digital output signal corresponding to the digital code during a successive approximation register (SAR) analog-digital conversion interval, and the digital output signal corresponding to an average of first and second digital control signals during a delta sigma analog-digital conversion interval, wherein the first and second comparison signals are respectively fed back to the first and second feedback capacitors. The analog-digital converter may be included in various electronic devices, including communication devices.

First claim

What is claimed is:

1. An analog digital converter having multiple feedback, the analog digital converter, comprising:
a capacitor digital-analog converter, including a plurality of switches driven by a digital code and a plurality of capacitors respectively connected to the plurality of switches, wherein the capacitor digital-analog converter is configured to generate a residue voltage based on an analog input voltage and a voltage corresponding to the digital code;
first and second feedback capacitors each storing the residue voltage;
an integrator configured to generate an integral signal by integrating the residue voltage;
first and second comparators respectively configured to generate first and second comparison signals from the integral signal; and
a digital logic circuitry configured to receive the first and second comparison signals, and generate a digital output signal from the first and second comparison signals, the digital output signal corresponding to the digital code during a successive approximation register (SAR) analog-digital conversion interval, and the digital output signal corresponding to an average of first and second digital control signals during a delta sigma analog-digital conversion interval,
wherein the first and second comparison signals are respectively fed back to the first and second feedback capacitors by the first and second digital control signals.

2. The analog digital converter of claim 1 , further comprising:
a first feedback switch connected to the first feedback capacitor in series and driven by a first digital control signal corresponding to the first comparison signal; and
a second feedback switch connected to the second feedback capacitor in series and driven by a second digital control signal corresponding to the second comparison signal.

3. The analog digital converter of claim 2 , wherein the first feedback switch is connected to a ground voltage terminal or a reference voltage terminal to which a reference voltage is applied, in response to the first digital control signal, and
the second feedback switch is connected to the ground voltage terminal or the reference voltage terminal in response to the second digital control signal.

4. The analog digital converter of claim 1 , further comprising:
an integral capacitor connected between an output terminal of the integrator and a ground voltage terminal; and
a reset switch connected across the integral capacitor in parallel.

5. The analog digital converter of claim 4 , wherein the reset switch is driven by an SAR control signal that is activated whenever comparing operations of the first and second comparators are completed during the SAR analog-digital conversion interval.

6. The analog digital converter of claim 1 , wherein a first capacitance of the first feedback capacitor and a second capacitance of the second feedback capacitor are the same as each other.

7. The analog digital converter of claim 6 , wherein the plurality of switches comprise a least significant bit (LSB) switch driven by an LSB of the digital code,
the plurality of capacitors comprise an LSB capacitor connected to the LSB switch, and
the first and second capacitances of the first and second feedback capacitors are the same as a capacitance of the LSB capacitor.

8. The analog digital converter of claim 1 , further comprising:
a first integral capacitor connected between a first output terminal of the integrator and a ground voltage terminal;
a first reset switch connected across the first integral capacitor in parallel;
a second integral capacitor connected between a second output terminal of the integrator and the ground voltage terminal; and
a second reset switch connected across the second integral capacitor in parallel.

9. The analog digital converter of claim 8 , wherein the first and second reset switches are driven by an SAR control signal that is activated whenever comparing operations of the first and second comparators are completed during an SAR analog-digital conversion interval.

10. The analog digital converter of claim 1 , wherein each of the plurality of switches is connected to an input voltage terminal to which the analog input voltage is applied, a reference voltage terminal to which a reference voltage is applied, or a ground voltage terminal, in response to the digital code, during the SAR analog-digital conversion interval.

11. The analog digital converter of claim 1 , wherein the analog digital converter operates at a Nyquist rate with respect to the analog input voltage.

12. A communication device comprising:
an analog-digital converter having multiple feedback and configured to convert an analog input signal to a digital output signal based on a reference voltage, wherein the analog input signal is produced from a communication signal received by the communication device; and
a reference voltage generator providing the reference voltage to the analog-digital converter, wherein:
the analog-digital converter comprises:
a capacitor digital-analog converter configured to receive the reference voltage, the analog input signal, and a digital code, and to generate a residue voltage based on the reference voltage, a first voltage corresponding to the digital code, and a second voltage corresponding to the analog input signal;
first and second feedback capacitors each storing the residue voltage;
an integrator configured to generate an integral signal by integrating the residue voltage; and
first and second comparators configured to respectively generate first and second comparison signals from the integral signal, and

the first and second comparison signals are respectively fed back to the first and second feedback capacitors.

13. The communication device of claim 12 , further comprising digital logic configured to receive the first and second comparison signals, generate the digital code in a successive approximation register (SAR) analog-digital conversion interval, and generate first and second digital control signals respectively corresponding to the first and second comparison signals in a delta sigma analog-digital conversion interval.

14. The communication device of claim 13 , wherein the capacitor digital-analog converter comprises:
a plurality of switches each connected to an input voltage terminal to which the analog input signal is applied, a reference voltage terminal to which the reference voltage is applied, or a ground voltage terminal, in response to the digital code in the SAR analog-digital conversion interval; and
a plurality of capacitors respectively connected to the plurality of switches in series.

15. The communication device of claim 13 , wherein the analog-digital converter further comprises:
a first feedback switch connected to the first feedback capacitor in series and driven by the first digital control signal; and
a second feedback switch connected to the second feedback capacitor in series and driven by the second digital control signal.

16. The communication device of claim 12 , wherein the analog-digital converter operates at a Nyquist rate with respect to the second voltage.

17. A device comprising:
a plurality of switches each connected, in response to a digital code supplied to the switches, to one of an input voltage terminal to which an analog input signal is applied, a reference voltage terminal to which a reference voltage is applied, and a ground voltage terminal;
a plurality of capacitors each having a first terminal connected to at least one of the plurality of switches and further having a second terminal, wherein

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sang-Heon
• Choi Michael

Classifications

• H03M3/46

  using a combination of at least one delta-sigma modulator in series with at least one analogue/digital converter of a different type · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H04B1/16

  Circuits · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M3/494

  Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems · CPC title