Cancel and replay protocol scheme to improve ordered bandwidth

Patent metadata

Field	Value
Publication number	US-10540316-B2
Application number	US-201715856799-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

Systems, apparatuses, and methods for implementing a cancel and replay mechanism for ordered requests are disclosed. A system includes at least an ordering master, a memory controller, a coherent slave coupled to the memory controller, and an interconnect fabric coupled to the ordering master and the coherent slave. The ordering master generates a write request which is forwarded to the coherent slave on the path to memory. The coherent slave sends invalidating probes to all processing nodes and then sends an indication that the write request is globally visible to the ordering master when all cached copies of the data targeted by the write request have been invalidated. In response to receiving the globally visible indication, the ordering master starts a timer. If the timer expires before all older requests have become globally visible, then the write request is cancelled and replayed to ensure forward progress in the fabric and avoid a potential deadlock scenario.

First claim

What is claimed is:

1. A system comprising:
an ordering master unit;
a coherent slave unit;
a memory controller coupled to the coherent slave unit; and
an interconnect fabric coupled to the ordering master unit and the coherent slave unit;
wherein the system is configured to:
send a write request, without corresponding write data, to the coherent slave unit from the ordering master unit;
start a timer, by the ordering master unit, responsive to receiving an indication, from the coherent slave unit, that the write request is globally visible;
cancel the write request responsive to determining:
the timer has expired; and
at least one older write request is still not globally visible; and

replay the write request by resending the write request from the ordering master unit to the coherent slave unit responsive to cancelling the write request.

2. The system as recited in claim 1 , wherein the ordering master unit is configured to cancel the write request by sending, to the coherent slave unit, a cancel indication that identifies the write request.

3. The system as recited in claim 1 , wherein the ordering master unit is further configured to send an indication that the older write request can be committed, along with the write data of the write request, to the coherent slave unit responsive to all older write requests being globally visible prior to the timer expiring.

4. The system as recited in claim 1 , wherein the ordering master unit is configured to provide commit indications for write requests in age order.

5. The system as recited in claim 4 , wherein the coherent slave unit is further configured to execute address matching requests in age order.

6. The system as recited in claim 1 , wherein the coherent slave unit is configured to write back any modified data to memory which was received via a probe response responsive to the write request being cancelled.

7. The system as recited in claim 1 , wherein the ordering master unit is further configured to issue requests to the interconnect fabric without waiting for prior requests to become globally ordered.

8. A method comprising:
sending a write request, without corresponding write data, to a coherent slave unit from an ordering master unit;
starting a timer, by the ordering master unit, responsive to receiving an indication, from the coherent slave unit, that the write request is globally visible;
cancelling the write request responsive to determining:
the timer has expired; and
at least one older write request is still not globally visible; and

replaying the write request by resending the write request from the ordering master unit to the coherent slave unit responsive to cancelling the write request.

9. The method as recited in claim 8 , further comprising cancelling the write request by sending, to the coherent slave unit, a cancel indication that identifies the write request.

10. The method as recited in claim 8 , further comprising sending an indication that the older write request can be committed, along with the write data of the write request, to the coherent slave unit responsive to all older write requests being globally visible prior to the timer expiring.

11. The method as recited in claim 8 , further comprising providing commit indications for write requests in age order.

12. The method as recited in claim 11 , further comprising executing address matching requests in age order.

13. The method as recited in claim 8 , further comprising writing back any modified data to memory which was received via a probe response responsive to the write request being cancelled.

14. The method as recited in claim 8 , further comprising issuing requests to the interconnect fabric without waiting for prior requests to become globally ordered.

15. An apparatus comprising:
an ordering master unit; and
a coherent slave unit;
wherein the apparatus is configured to:
send a write request, without corresponding write data, to the coherent slave unit from the ordering master unit;
start a timer, by the ordering master unit, responsive to receiving an indication, from the coherent slave unit, that the write request is globally visible;
cancel the write request responsive to determining:
the timer has expired; and
at least one older write request is still not globally visible; and

replay the write request by resending the write request from the ordering master unit to the coherent slave unit responsive to cancelling the write request.

16. The apparatus as recited in claim 15 , wherein the ordering master unit is configured to cancel the write request by sending, to the coherent slave unit, a cancel indication that identifies the write request.

17. The apparatus as recited in claim 15 , wherein the ordering master unit is further configured to send an indication that the older write request can be committed, along with the write data of the write request, to the coherent slave unit responsive to all older write requests being globally visible prior to the timer expiring.

18. The apparatus as recited in claim 15 , wherein the ordering master unit is configured to provide commit indications for write requests in age order.

19. The apparatus as recited in claim 18 , wherein the coherent slave unit is configured to execute address matching requests in age order.

20. The apparatus as recited in claim 15 , wherein the ordering master unit is further configured to issue requests to the interconnect fabric without waiting for prior requests to become globally ordered.

21. The system as recited in claim 1 , wherein the write request is globally visible when all cached copies of data targeted by the write request have been invalidated.

22. The method as recited in claim 8 , wherein the write request is globally visible when all cached copies of data targeted by the write request have been invalidated.

23. The apparatus as recited in claim 15 , wherein the write request is globally visible when all cached copies of data targeted by the write request have been invalidated.

Assignees

• Advanced Micro Devices Inc

Inventors

• Kalyanasundharam Vydhyanathan
• Morton Eric Christopher
• Yang Chen-Ping
• Apte Amit P
• Cooper Elizabeth M

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F13/1663 Primary

  Access to shared memory · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F12/0806

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title