Program event recording within a transactional environment

Patent metadata

Field	Value
Publication number	US-9317460-B2
Application number	US-201213524903-A
Country	US
Kind code	B2
Filing date	Jun 15, 2012
Priority date	Jun 15, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.

First claim

What is claimed is:

1. A computer program product for controlling transactional execution in a computing environment, the computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
initiating, by a processor, a transaction within a computing environment, the transaction effectively delaying committing transactional stores to main memory until completion of a selected transaction, and wherein presentation of interrupts for the transaction is managed by one or more controls, the one or more controls having state associated therewith;
presenting an interrupt for the transaction based on detecting a program event recording (PER) event and the state having a first value, PER being defined as presenting an interrupt based on detecting a PER event, the interrupt causing an address to be saved of a next transaction instruction to be executed; and
suppressing PER event detection for the transaction based on the state having a second value, wherein the suppressing comprises ignoring one or more PER event masks used to control one or more PER events for the processor, the ignoring preventing the one or more PER events from operating as defined during transactional-execution mode of the processor, and wherein the suppressing PER event detection avoids presenting interrupts that would have been presented had PER event detection not been suppressed and a PER event detected.

2. The computer program product of claim 1 , wherein the method further comprises re-executing the transaction based on the interrupt, and wherein the state has the second value indicating suppression of PER event detection, wherein presentation of another interrupt based on another PER event is prevented.

3. The computer program product of claim 1 , wherein the one or more controls comprise an event suppression control to specify a suppression of selected PER events, and a transaction end event control to trigger an event based on the selected transaction ending.

4. The computer program product of claim 3 , wherein the selected PER events include one or more events of the following events: successful-branching event, instruction-fetch event, storage-alteration event, store-using-real-address event, or zero-address-detection event.

5. The computer program product of claim 4 , wherein the following events further include an instruction fetch nullification event, based on the transaction not being an outermost transaction.

6. The computer program product of claim 3 , wherein the method further comprises:
based on the event suppression control being set, inhibiting PER events, except the transaction end event, independent of accessing task structures in which current PER settings are maintained.

7. The computer program product of claim 1 , wherein the method further comprises detecting execution of a transaction end for the selected transaction, wherein based on the detecting, the one or more controls are to be reset.

8. The computer program product of claim 7 , wherein the selected transaction comprises an outermost transaction.

9. The computer program product of claim 1 , wherein the one or more controls are maintained in a control register of the processor.

10. The computer program product of claim 2 , wherein the other PER event is a same event as the PER event or a different event than the PER event.

11. A computer system for controlling transactional execution in a computing environment, the computer system comprising:
a memory; and
a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
initiating, by a processor, a transaction within a computing environment, the transaction effectively delaying committing transactional stores to main memory until completion of a selected transaction, and wherein presentation of interrupts for the transaction is managed by one or more controls, the one or more controls having state associated therewith;
presenting an interrupt for the transaction based on detecting a program event recording (PER) event and the state having a first value, PER being defined as presenting an interrupt based on detecting a PER event, the interrupt causing an address to be saved of a next transaction instruction to be executed; and
suppressing PER event detection for the transaction based on the state having a second value, wherein the suppressing comprises ignoring one or more PER event masks used to control one or more PER events for the processor, the ignoring preventing the one or more PER events from operating as defined during transactional-execution mode of the processor, and wherein the suppressing PER event detection avoids presenting interrupts that would have been presented had PER event detection not been suppressed and a PER event detected.

12. The computer system of claim 11 , wherein the one or more controls comprise an event suppression control to specify a suppression of selected PER events, and a transaction end event control to trigger an event based on the selected transaction ending.

13. The computer system of claim 12 , wherein the selected PER events include one or more events of the following events: successful-branching event, instruction-fetch event, storage-alteration event, store-using-real-address event, or zero-address-detection event.

14. The computer system of claim 12 , wherein the method further comprises:
based on the event suppression control being set, inhibiting PER events, except the transaction end event, independent of accessing task structures in which current PER settings are maintained.

15. The computer system of claim 11 , wherein the method further comprises detecting execution of a transaction end for the selected transaction, wherein based on the detecting, the one or more controls are to be reset.

16. The computer system of claim 11 , wherein the one or more controls are maintained in a control register of the processor.

17. The computer system of claim 11 , wherein the method further comprises re-executing the transaction based on the interrupt, and wherein the state has the second value indicating suppression of PER event detection, wherein presentation of another interrupt based on another PER event is prevented, and wherein the other PER event is a same event as the PER event or a different event than the PER event.

Assignees

• Greiner Dan F
• Jacobi Christian
• Osisek Damian L
• Slegel Timothy J
• IBM

Inventors

• Greiner Dan F
• Jacobi Christian
• Osisek Damian L
• Slegel Timothy J

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F11/3636

  by tracing the execution of the program · CPC title

• G06F9/466

  Transaction processing · CPC title