Evaluation apparatus including a plurality of insulating portions surrounding a probe and semiconductor device evaluation method based thereon

Patent metadata

Field	Value
Publication number	US-10539607-B2
Application number	US-201715588783-A
Country	US
Kind code	B2
Filing date	May 8, 2017
Priority date	Sep 28, 2016
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

An evaluation apparatus includes an insulating plate, a plurality of probes fixed to the insulating plate, an insulating portion having a connection portion connected to the insulating plate in a detachable manner and a tip portion continuous with the connection portion, the tip portion being narrower than the connection portion, an insulator formed by combining the insulating portions to surround the plurality of probes in planar view, and an evaluation unit for passing currents through the plurality of probes to evaluate electrical characteristics of an object to be measured.

First claim

What is claimed is:

1. An evaluation apparatus comprising:
an insulating plate;
a plurality of probes fixed to the insulating plate;
a plurality of insulating portions each having a connection portion connected to the insulating plate in a detachable manner and a tip portion continuous with the connection portion, the tip portions being narrower than the connection portions;
an insulator formed by combining the insulating portions to surround the plurality of probes in plan view; and
an evaluation unit for passing currents through the plurality of probes to evaluate electrical characteristics of an object to be measured.

2. The evaluation apparatus according to claim 1 , further comprising:
a chuck stage, wherein
a lower surface of each tip portion faces a surface of the chuck stage.

3. The evaluation apparatus according to claim 1 , wherein an internal wall surface of each tip portion is a slope, and each tip portion has a tapered shape.

4. The evaluation apparatus according to claim 1 , wherein a groove is formed in a lower surface of each tip portion, and divides the lower surface into a plurality of lower surfaces.

5. The evaluation apparatus according to claim 1 , wherein a lower surface of each tip portion is rectangular in plan view.

6. The evaluation apparatus according to claim 1 , wherein an external wall surface of each tip portion is a slope, and the tip portion has a tapered shape.

7. The evaluation apparatus according to claim 1 , wherein a recessed portion is formed in a lower surface of each tip portion.

8. The evaluation apparatus according to claim 1 , wherein the insulator is made of silicone rubber.

9. The evaluation apparatus according to claim 1 , further comprising:
a protective member provided on a lower surface of each tip portion to protect the lower surface.

10. The evaluation apparatus according to claim 1 , wherein the insulator fits into a groove portion provided in a lower surface of the insulating plate.

11. The evaluation apparatus according to claim 10 , wherein the insulating plate has a spare groove portion to which the insulator does not fit.

12. The evaluation apparatus according to claim 1 , wherein the insulator fits into at least one through-hole provided in the insulating plate.

13. The evaluation apparatus according to claim 12 , wherein the insulating plate has a through-hole to which the insulator does not fit.

14. The evaluation apparatus according to claim 12 , wherein the at least one through-hole comprises a plurality of through-holes provided in a non-looped shape.

15. The evaluation apparatus according to claim 1 , wherein two adjacent insulating portions of the plurality of insulating portions fit to each other.

16. The evaluation apparatus according to claim 1 , further comprising:
a plurality of sockets fixed to the insulating plate, wherein
the plurality of probes are fixed to the plurality of sockets.

17. The evaluation apparatus according to claim 1 , further comprising:
an electromagnetic shield provided inside or on a surface of the insulator.

18. A semiconductor device evaluation method for evaluating electrical characteristics of a semiconductor device, comprising:
bringing a plurality of probes fixed to an insulating plate into contact with an active area of the semiconductor device;
bringing an insulator, which is comprised on a plurality of insulating portions each having a tip portion and a connection portion, and which is connected to the insulating plate in a detachable manner to surround the plurality of probes into contact with part of a termination region surrounding the active area of the semiconductor device directly or with a protective member interposed therebetween; and
passing currents through the plurality of probes.

Assignees

• Mitsubishi Electric Corp

Inventors

• Okada Akira
• Yamashita Kinya
• Ueno Masaki

Classifications

• H10P72/7604

  the wafers being placed on a susceptor, stage or support · CPC title

• H10P72/78

  using vacuum or suction, e.g. Bernoulli chucks · CPC title

• G01R31/44 Primary

  Testing lamps · CPC title

• G01R31/2601 Primary

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title

• G01R31/261 Primary

  for measuring break-down voltage or punch through voltage therefor · CPC title