Apparatus and method for correcting baseline wander and offset insertion in AC coupling circuits

Patent metadata

Field	Value
Publication number	US-9800218-B1
Application number	US-201615193716-A
Country	US
Kind code	B1
Filing date	Jun 27, 2016
Priority date	Jun 27, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

The disclosure relates to an alternating current (AC) coupling circuit including first and second capacitors having first and second input terminals configured to receive an input differential signal and generate an output differential signal at first and second output terminals of the first and second capacitors. The AC coupling circuit further includes a baseline wander correction circuit configured to make the output differential signal resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data. The baseline wander correction circuit includes a differential difference amplifier (DDA) having a first differential input configured to receive the input differential signal, a differential output configured to generate a compensation differential signal, and a second differential input configured to receive the compensation differential signal. The compensation differential signal is applied to the output terminals of the first and second capacitors via a pair of resistors, respectively.

First claim

What is claimed is:

1. An apparatus, comprising:
a first capacitor including a first input terminal and a first output terminal;
a second capacitor including a second input terminal and a second output terminal; and
a baseline wander correction circuit configured to:
receive an input differential signal across the first and second input terminals of the first and second capacitors;
generate a compensation differential signal based on the input differential signal, wherein the compensation differential signal produces an output differential signal across the first and second output terminals of the first and second capacitors that is resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data;
receive an input offset differential signal; and
impress an offset on the output differential signal based on the input offset differential signal.

2. The apparatus of claim 1 , wherein the baseline wander correction circuit is configured to impress the offset on the output differential signal without affecting the resistance of the output differential signal to baseline wander.

3. An apparatus, comprising:
a first capacitor including a first input terminal and a first output terminal;
a second capacitor including a second input terminal and a second output terminal; and
a baseline wander correction circuit configured to:
receive an input differential signal across the first and second input terminals of the first and second capacitors; and
generate a compensation differential signal based on the input differential signal, wherein the compensation differential signal produces an output differential signal across the first and second output terminals of the first and second capacitors that is resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data, wherein the baseline wander correction circuit comprises a difference differential amplifier (DDA).

4. The apparatus of claim 3 , wherein the DDA includes a first differential input configured to receive the input differential signal.

5. The apparatus of claim 4 , wherein the DDA further comprises:
a differential output configured to generate the compensation differential signal; and
a second differential input configured to receive the compensation differential signal.

6. The apparatus of claim 5 , further comprising:
a first resistor coupled between a negative terminal of the differential output of the DDA and the first output terminal of the first capacitor; and
a second resistor coupled between a positive terminal of the differential output of the DDA and the second output terminal of the second capacitor.

7. The apparatus of claim 5 , wherein the DDA further comprises a third differential input configured to receive an input offset differential signal, wherein the DDA is further configured to impress an offset on the output differential signal based on the input offset differential signal.

8. The apparatus of claim 1 , further comprising a variable gain amplifier (VGA) including an input differential input coupled to the first and second output terminals of the first and second capacitors, respectively.

9. The apparatus of claim 1 , further comprising an equalizer including an input differential input configured to receive a differential signal based on the output differential signal.

10. A method, comprising:
receiving an input differential signal across first and second input terminals of first and second capacitors;
generating a compensation differential signal based on the input differential signal, wherein the compensation differential signal produces an output differential signal across first and second output terminals of the first and second capacitors that is resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data;
receiving an input offset differential signal; and
impressing an offset on the output differential signal based on the input offset differential signal.

11. The method of claim 10 , wherein impressing the offset on the output differential signal comprise impressing the offset on the output differential signal without affecting the resistance of the output differential signal to baseline wander.

12. The method of claim 10 , wherein a difference between the compensation differential signal is substantially the same as a difference between the input differential signal.

13. A method, comprising:
receiving an input differential signal across first and second input terminals of first and second capacitors;
generating a compensation differential signal based on the input differential signal, wherein the compensation differential signal produces an output differential signal across first and second output terminals of the first and second capacitors that is resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data; and
applying the compensation differential signal to the first and second output terminals of the first and second capacitors via first and second resistors, respectively.

14. A method, comprising:
receiving an input differential signal across first and second input terminals of first and second capacitors;
generating a compensation differential signal based on the input differential signal, wherein the compensation differential signal produces an output differential signal across first and second output terminals of the first and second capacitors that is resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data;
receiving an input offset differential signal; and
impressing an offset on the compensation differential signal based on the input offset differential signal.

15. The method of claim 10 , further comprising amplifying the output differential signal.

16. The method of claim 15 , further comprising equalizing the amplified output differential signal.

17. The method of claim 10 , further comprising equalizing the output differential signal.

18. An apparatus, comprising:
means for receiving an input differential signal across first and second input terminals of first and second capacitors;
means for generating a compensation differential signal based on the input differential signal, wherein the compensation differential signal produces an output differential signal across first and second output terminals of the first and second capacitors that is resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data;
means for receiving an input offset differential signal; and
means for impressing an offset on the output differential signal based on the input offset differential signal.

19. The apparatus of claim 18 , wherein the means for impressing the offset on the output differential signal comprise means for impressing the offset on the output differential signal without affecting the resistance of the output differential signal to baseline wander.

20. The apparatus of claim 18 , wherein a difference between the compensation differential signal is substantially the same as a difference between the input differential signal.

21. An apparatus, comprising:
means for receiving an input differential signal across first and second input terminals of first and second capacitors;
means for generating a compensation different

Assignees

• Qualcomm Inc

Inventors

• Rasmus Todd Morgan

Classifications

• H03F2203/45042

  One or more resistors are added or changed as balancing to reduce the offset of the dif amp · CPC title

• H03F2203/45596

  the IC comprising one or more biasing resistors · CPC title

• H03F2203/45152

  Balancing means being added at the input of a dif amp to reduce the offset of the dif amp · CPC title

• H03F2203/45156

  At least one capacitor being added at the input of a dif amp · CPC title

• H03F3/45704

  Controlling the input circuit of the differential amplifier · CPC title