Method for forming solder bumps using sacrificial layer

Patent metadata

Field	Value
Publication number	US-10535592-B2
Application number	US-201815936014-A
Country	US
Kind code	B2
Filing date	Mar 26, 2018
Priority date	Oct 30, 2015
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.

First claim

What is claimed as new is:

1. A circuit comprising:
a plurality of spaced apart electrically conductive contact pads located directly on a surface of a substrate;
a solder resist layer located between each electrically conductive contact pad and located directly on the substrate, wherein a portion of the solder resist layer is disposed onto a topmost surface of each electrically conductive pad;
a solder bump disposed on a physically exposed surface of each electrically conductive pad and partially disposed on a topmost surface of each solder resist layer, wherein the solder bump comprises tin that is alloyed with at least a first metal selected from a rare earth metal, wherein the rare earth metal is non-homogeneously dispersed throughout the solder bump; and
a metallic layer composed of at least the first metal located between the solder bump and each electrically conductive pad.

2. The circuit of claim 1 , wherein the substrate is selected from the group consisting of an organic substrate, a glass interposer, and a silicon interposer.

3. The circuit of claim 1 , wherein the solder resist layer has a height that is greater than a height of each electrically conductive contact pad.

4. The circuit of claim 3 , wherein the solder bond has a height that is greater than the height of the solder resist layer.

5. The circuit of claim 1 , wherein the tin is further alloyed with a second metal different from the first metal.

6. The circuit of claim 5 , wherein the second metal is selected from at least one of Cu, Zn, Ag, Au, and Bi.

7. The circuit of claim 1 , wherein the rare earth metal comprises scandium, yttrium, lanthanum, cerium, praseodymium, promethium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or lutetium.

8. The circuit of claim 1 , wherein the solder bump comprises up to 3 weight percent of the first metal.

9. The circuit of claim 1 , wherein the first metal consists of 0.5 to 2 weight percent of one of lutetium, lanthanum, cerium, ytterbium, and neodymium.

10. The circuit of claim 1 , wherein the first metal consists of 0.25 to 1 weight percent of a combination of lanthanum and cerium.

11. The circuit of claim 1 , wherein the first metal consists of 0.05 to 1 weight percent of cerium.

12. A circuit comprising:
a plurality of spaced apart electrically conductive contact pads located directly on a surface of a substrate;
a solder resist layer located between each electrically conductive contact pad and located directly on the substrate, wherein a portion of the solder resist layer is disposed onto a topmost surface of each electrically conductive pad; and
a solder bump disposed on a physically exposed surface of each electrically conductive pad and partially disposed on a topmost surface of each solder resist layer, wherein the solder bump comprises an alloy of tin and a rare earth metal, wherein the rare earth metal is non-homogeneously dispersed throughout the solder bump.

13. The circuit of claim 12 , wherein the substrate is selected from the group consisting of an organic substrate, a glass interposer, and a silicon interposer.

14. The circuit of claim 12 , wherein the solder resist layer has a height that is greater than a height of each electrically conductive contact pad.

15. The circuit of claim 14 , wherein the solder bond has a height that is greater than the height of the solder resist layer.

16. The circuit of claim 12 , wherein the tin is further alloyed with at least one of Cu, Zn, Ag, Au, and Bi.

17. The circuit of claim 12 , wherein the rare earth metal comprises scandium, yttrium, lanthanum, cerium, praseodymium, promethium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or lutetium.

Assignees

• IBM

Inventors

• Lewandowski Eric P
• Nah Jae-Woong
• Sorce Peter J

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W70/69

  Insulating materials thereof · CPC title