Multi-stage decoder

Patent metadata

Field	Value
Publication number	US-2016179620-A1
Application number	US-201615061246-A
Country	US
Kind code	A1
Filing date	Mar 4, 2016
Priority date	Jun 30, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

An apparatus includes a memory die including a group of storage elements and one or more unallocated redundant columns. A number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die. The apparatus further includes a controller coupled to the memory. The controller is configured to receive data and redundancy information associated with the data from the memory. The data includes a first bit, and the redundancy information includes a second bit. The redundancy information is sensed from the one or more unallocated redundant columns and has a size that is based on the number of one or more bad columns. The controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.

First claim

What is claimed is:

1 . An apparatus comprising:
a memory die including a group of storage elements and one or more unallocated redundant columns, wherein a number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die; and a controller coupled to the memory, the controller configured to receive data and redundancy information associated with the data from the memory, the data including a first bit and the redundancy information including a second bit, the redundancy information sensed from the one or more unallocated redundant columns and having a size that is based on the number of one or more bad columns, wherein the controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.

2 . The apparatus of claim 1 , further comprising a second memory die including a second set of one or more bad columns, wherein a number of the second set of one or more bad columns is different than the number of unallocated redundant columns of the memory die.

3 . The apparatus of claim 2 , wherein the second memory die further includes a second set of one or more unallocated redundant columns configured to store second redundancy information having a different data size than the redundancy information.

4 . The apparatus of claim 1 , wherein the controller includes a control circuit configured to select a subset of bits of the data during an encoding process, the subset of bits including the first bit.

5 . The apparatus of claim 4 , wherein the controller further includes an exclusive-or (XOR) circuit configured to perform an XOR operation based on the subset of bits to generate the second bit.

6 . The apparatus of claim 1 , wherein the controller includes a bit-flipping circuit configured to modify the value of the first bit from a first logic value to a second logic value.

7 . The apparatus of claim 6 , wherein the controller further includes a decoder coupled to the bit-flipping circuit.

8 . The apparatus of claim 7 , wherein the decoder is configured to receive the modified value from the bit-flipping circuit and to initiate a decoding process to decode the data using the modified value.

9 . A method of operation of a data storage device that includes a memory and a controller, the method comprising:
receiving a representation of a codeword from the memory, the representation of the codeword including a first bit; receiving parity information from the memory, the parity information associated with the codeword and sensed from a set of redundant columns of the memory, the parity information including a second bit; and determining a value of the first bit based on one or more parity check conditions associated with the second bit.

10 . The method of claim 9 , wherein the memory includes an allocated redundant column.

11 . The method of claim 9 , wherein a storage element of a set of redundant columns of the memory replaces a storage element of a bad column of the memory.

12 . The method of claim 9 , wherein determining the value of the first bit includes changing the first bit from a first logic value to a second logic value.

13 . The method of claim 12 , further comprising:
generating modified data that includes the changed first bit; and providing the modified data from a bit-flipping circuit to a decoder of the controller to initiate a decoding process.

14 . The method of claim 9 , wherein the second bit is generated based on an operation associated with a subset of bits of the codeword that includes the first bit.

15 . The method of claim 14 , wherein the second bit is based on an exclusive-or (XOR) operation of the subset of bits.

16 . The method of claim 15 , wherein determining the value of the first bit includes modifying the value of the first bit in response to determining that the modified value satisfies the XOR operation.

17 . The method of claim 9 , wherein a number of bits of the parity information corresponds to a number of columns of the set of redundant columns.

18 . The method of claim 17 , wherein a dimension of a parity check matrix associated with the codeword is based on a number of bits of the codeword and the number of bits of the parity information, and further comprising detecting decoding convergence of decoding the codeword independently of satisfaction of parity check conditions corresponding to the parity information.

19 . The method of claim 9 , wherein the codeword is a low-density parity check (LDPC) codeword.

20 . A method of operation of a data storage device that includes a memory and a controller, the method comprising:
after encoding data to generate a codeword, generating parity information including a parity bit based on a subset of bits of the codeword; sending the codeword to be stored at a group of storage elements of the memory; and sending the parity bit to be stored at a redundant column associated with the group of storage elements.

21 . The method of claim 20 , wherein a number of bits of the subset is based on a number of unused redundant columns associated with the group of storage elements.

22 . The method of claim 20 , wherein generating the parity bit includes performing an exclusive-or (XOR) operation based on the subset of bits.

23 . The method of claim 22 , wherein the parity bit is based on the subset of bits due to being generated using the XOR operation.

Assignees

• Sandisk Technologies Inc

Inventors

• Bazarsky Alexander
• Zamir Ran
• Sharon Eran
• Alrod Idan

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/064

  Management of blocks · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title