Sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-10530385-B2
Application number	US-201716312865-A
Country	US
Kind code	B2
Filing date	Jun 22, 2017
Priority date	Jun 23, 2016
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A Sigma-Delta (ΣΔ) modulator for converting an analog input signal having a frequency bandwidth around a variable center frequency f 0 to a digital output signal at a sampling frequency f s . The ΣΔ modulator comprises a quantizer ( 420 ) for generating the digital output signal and a loop filter for shaping the quantization noise. The loop filter comprises at least one subfilter ( 430, 410 ) centered around a frequency f 0 and constant noise shaping coefficients ( 451, 452, 453 ). The ΣΔ modulator further comprises a tunable delay element ( 455 ), a frequency adjuster ( 480 ) for adjusting the sampling frequency f s such that the normalized center frequency f 0 /f s is constant, and a delay adjuster ( 490 ) for adjusting the loop delay t d implemented by the quantizer and the tunable delay element ( 455 ), such that the normalized loop delay t d /T s falls in a predetermined range [t min , t max ], where T s =1/f s .

First claim

The invention claimed is:

1. A Sigma-Delta (ΣΔ) modulator for converting an analog input signal having a frequency bandwidth around a variable center frequency f 0 to a digital output signal at a sampling frequency f s , the ΣΔ modulator comprising
a quantizer for generating the digital output signal,
a loop filter for shaping the quantization noise, the loop filter comprising
at least one subfilter centered around a frequency f 0 , and
noise shaping coefficients,

the ΣΔ modulator being characterized in that:
the noise shaping coefficients are constant and independent of the center frequency f 0 ;
the ΣΔ modulator further comprises
a tunable delay element;
a frequency adjuster for adjusting the sampling frequency f s such that the normalized center frequency f 0 /f s is constant;
a delay adjuster for adjusting the loop delay t d implemented by the quantizer and the tunable delay element, such that the normalized loop delay t d /T s falls in a predetermined range [t min , t max ], where T s =1/f s .

2. The ΣΔ modulator according to claim 1 , wherein the predetermined range [t min , t max ] is independent on the center frequency f 0 and the loop delay t d is adjusted to a value that is a function of the center frequency f 0 and the sampling frequency f s .

3. The ΣΔ modulator according to claim 1 , wherein t min =t max .

4. The ΣΔ modulator according to claim 1 , wherein the tunable delay element comprises a plurality of cascaded latches and the delay adjuster is configured to adjust the loop delay t d to a number of half of a clock period of a clock signal controlling the plurality of cascaded latches.

5. The ΣΔ modulator according to claim 4 , the delay adjuster is configured to send to each latch of the plurality of cascaded latches a clock signal selected from the group comprising the clock signal and the inversed clock signal.

6. The ΣΔ modulator according to claim 1 , wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

7. A Sigma-Delta Analog-to-Digital converter (ΣΔ ADC) comprising a Sigma-Delta modulator according to claim 1 .

8. A telecommunication device comprising a radio interface for receiving a radio signal and an Analog-to-Digital converter according to claim 7 for converting the radio signal to a digital signal.

9. A method for converting an analog input signal having a frequency bandwidth around a variable center frequency f 0 to a digital output signal at a sampling frequency f s by a Sigma-Delta (ΣΔ) modulator, the ΣΔ modulator comprising a quantizer and a loop filter for shaping the quantization noise, the loop filter comprising at least one subfilter centered around frequency f 0 and noise shaping coefficients,
the method comprising,
processing by the ΣΔ modulator said analog input signal for generating said digital output signal,
the method being characterized in that:
the processing is performed using constant noise shaping coefficients which are independent of the center frequency f 0 ;
the ΣΔ modulator further comprises a tunable delay element;

and in that the method further comprises:
adjusting the sampling frequency f s such that the normalized center frequency f 0 /f s is constant,
adjusting the loop delay t d implemented by the quantizer and the tunable delay element, such that the normalized loop delay t d /T s falls in a
predetermined range [t min , t max ], where T s =1/f s .

10. The method according to claim 9 , wherein t min =t max .

11. The ΣΔ modulator according to claim 2 , wherein t min =t max .

12. The ΣΔ modulator according to claim 2 , wherein the tunable delay element comprises a plurality of cascaded latches and the delay adjuster is configured to adjust the loop delay t d to a number of half of a clock period of a clock signal controlling the plurality of cascaded latches.

13. The ΣΔ modulator according to claim 3 , wherein the tunable delay element comprises a plurality of cascaded latches and the delay adjuster is configured to adjust the loop delay t d to a number of half of a clock period of a clock signal controlling the plurality of cascaded latches.

14. The ΣΔ modulator according to claim 2 , wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

15. The ΣΔ modulator according to claim 3 , wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

16. The ΣΔ modulator according to claim 4 , wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

17. The ΣΔ modulator according to claim 5 , wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

18. A Sigma-Delta Analog-to-Digital converter (ΣΔ ADC) comprising a Sigma-Delta modulator according to claim 2 .

19. A Sigma-Delta Analog-to-Digital converter (ΣΔ ADC) comprising a Sigma-Delta modulator according to claim 3 .

20. A Sigma-Delta Analog-to-Digital converter (ΣΔ ADC) comprising a Sigma-Delta modulator according to claim 4 .

Assignees

• Univ Sorbonne
• Centre Nat Rech Scient

Inventors

• Aboushady Hassan
• Badran Tamer
• Sayed Alhassan

Classifications

• H03M3/496 Primary

  Details of sampling arrangements or methods · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/402

  Arrangements specific to bandpass modulators · CPC title

• H03M3/396

  among different frequency bands · CPC title

• H03M3/43 Primary

  the quantiser being a single bit one · CPC title