Double gate transistor device and method of operating

Patent metadata

Field	Value
Publication number	US-10530360-B2
Application number	US-201715439706-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Feb 29, 2016
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

First claim

What is claimed is:

1. A method comprising:
switching on a transistor device by generating a first conducting channel by driving a first gate electrode at a first slew rate and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode at a second slew rate greater than the first slew rate,
wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device, wherein driving the first gate electrode comprises increasing a first drive signal from a first off-level to a first on-level, wherein driving the second gate electrode comprises increasing a second drive signal from a second off-level to a second on-level, and wherein the second off-level is different from the first off-level.

2. The method of claim 1 ,
wherein the transistor device is a field-effect controlled transistor device,
wherein generating the first conducting channel comprises generating the first conducting channel in a body region,
wherein generating the second conducting channel comprises generating the second conducting channel in the body region,
wherein the first gate electrode is dielectrically insulated from the body region by a first gate dielectric,
wherein the second gate electrode is dielectrically insulated from the body region by a second gate dielectric,
wherein the second gate electrode is separated from the first gate electrode by a separation layer, and
wherein the body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

3. The method of claim 1 , wherein the transistor device comprises a HEMT (High Electron Mobility Transistor) device.

4. The method of claim 1 , wherein the transistor device comprises a GIT (Gate Injection Transistor) device.

5. The method of claim 4 , wherein the GIT device comprises a first injection gate adjoining the first gate electrode and a second injection gate adjoining the second gate electrode.

6. The method of claim 4 ,
wherein the GIT device comprises only one injection gate.

7. The method of claim 1 , wherein driving the first gate electrode comprises clamping the second gate electrode to the second on-level.

8. The method of claim 1 , further comprising:
detecting a change in an operation state of the transistor device,
wherein detecting the operation state comprises monitoring at least one electrical parameter of the second gate electrode.

9. The method of claim 1 , further comprising:
switching off a transistor device by interrupting the first conducting channel via the first gate electrode; and
after interrupting the first conducting channel, interrupting the second conducting channel via the second gate electrode.

10. The method of claim 9 , wherein:
interrupting the first conducting channel via the first gate electrode comprises decreasing a first drive signal from a first on-level to a first off-level, and
interrupting the second conducting channel via the second gate electrode comprises decreasing a second drive signal between the second gate electrode and a source region from a second on-level to a second off-level.

11. A circuit comprising:
a transistor device configured to be switched on by generating a first conducting channel by driving a first gate electrode at a first slew rate, and before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode at a second slew rate greater than the first slew rate,
wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device, wherein driving the first gate electrode comprises increasing a first drive signal from a first off-level to a first on-level, wherein driving the second gate electrode comprises increasing a second drive signal from a second off-level to a second on-level, and wherein the second off-level is different from the first off-level.

12. The circuit of claim 11 ,
wherein the transistor device is a field-effect controlled transistor device,
wherein generating the first conducting channel comprises generating the first conducting channel in a body region,
wherein generating the second conducting channel comprises generating the second conducting channel in the body region,
wherein the first gate electrode is dielectrically insulated from the body region by a first gate dielectric,
wherein the second gate electrode is dielectrically insulated from the body region by a second gate dielectric,
wherein the second gate electrode is separated from the first gate electrode by a separation layer, and
wherein the body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

13. The circuit of claim 11 , wherein the transistor device comprises a HEMT (High Electron Mobility Transistor) device.

14. The circuit of claim 11 , wherein the transistor device comprises a GIT (Gate Injection Transistor) device.

15. The circuit of claim 14 , wherein the GIT device comprises a first injection gate adjoining the first gate electrode and a second injection gate adjoining the second gate electrode.

16. The circuit of claim 14 , wherein the GIT device comprises only one injection gate.

17. The circuit of claim 11 , wherein driving the first gate electrode comprises clamping the second gate electrode to the second on-level.

18. The circuit of claim 11 , further comprising a circuit configured to detect a change in an operation state of the transistor device, wherein detecting the operation state comprises monitoring at least one electrical parameter of the second gate electrode.

19. The circuit of claim 11 , wherein the transistor device is configured to be switched off by interrupting the first conducting channel via the first gate electrode, and after interrupting the first conducting channel, interrupting the second conducting channel via the second gate electrode.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Bina Markus
• Mauder Anton
• Barrenscheen Jens

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H03K2017/6878

  using multi-gate field-effect transistors · CPC title

• H03K17/567 Primary

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title