Reversed stack MTJ

Patent metadata

Field	Value
Publication number	US-10529916-B2
Application number	US-201715463500-A
Country	US
Kind code	B2
Filing date	Mar 20, 2017
Priority date	Sep 3, 2013
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

First claim

The invention claimed is:

1. An integrated circuit device, comprising:
a substrate;
a magnetic tunneling junction (MTJ) disposed over a surface of the substrate, the MTJ comprising:
a first ferromagnetic layer arranged over the surface of the substrate;
an insulating barrier layer arranged over the first ferromagnetic layer; and
a second ferromagnetic layer arranged over the insulating barrier layer, wherein the first ferromagnetic layer is connected to a bottom electrode and the second ferromagnetic layer is connected to a top electrode, and wherein the top electrode, the second ferromagnetic layer and the insulating barrier layer have substantially aligned sidewalls;
wherein the second ferromagnetic layer and the insulating barrier layer have a first width as measured between the substantially aligned sidewalls; and
wherein the first ferromagnetic layer has a second width measured between its outer sidewalls, wherein the second width is greater than the first width.

2. The integrated circuit device of claim 1 , wherein the first ferromagnetic layer is a free layer configured to switch between at least two different magnetic orientations, and the second ferromagnetic layer is a pinned layer having a fixed magnetic orientation.

3. The integrated circuit device of claim 1 , wherein the substantially aligned sidewalls of the insulating barrier layer and the second ferromagnetic layer are disposed on an upper surface of the first ferromagnetic layer.

4. The integrated circuit device of claim 1 , wherein the substantially aligned sidewalls of the insulating barrier layer and the second ferromagnetic layer are spaced apart from sidewalls of the first ferromagnetic layer.

5. The integrated circuit device of claim 4 , further comprising:
a first set of spacers resting on outer upper edges of first ferromagnetic layer, and extending upwardly along the substantially aligned sidewalls of the second ferromagnetic layer and the insulating barrier layer.

6. The integrated circuit device of claim 5 , wherein the bottom electrode has a third width between its outer sidewalls, the third width being greater than the second width.

7. The integrated circuit device of claim 5 , further comprising:
a second set of spacers resting on outer upper edges of the bottom electrode, and extending upwardly along outer sidewalls of first set of spacers.

8. The integrated circuit device of claim 1 , wherein at least one of the first ferromagnetic layer and the second ferromagnetic layer are made of NiFe, CoFe, or CoFeB.

9. The integrated circuit device of claim 5 , wherein the first set of spacers are formed from material selected from a group consisting of silicon nitride, silicon dioxide, and silicon oxynitride.

10. An integrated circuit device, comprising:
a substrate;
a first ferromagnetic layer disposed over the substrate;
an insulating barrier layer arranged over the first ferromagnetic layer;
a second ferromagnetic layer over the insulating barrier layer; wherein the insulating barrier layer and the second ferromagnetic layer have substantially aligned sidewalls which are disposed on an upper surface of the first ferromagnetic layer; and
a first sidewall spacer layer directly above the first ferromagnetic layer and covering the sidewalls of the insulating barrier layer.

11. The integrated circuit device of claim 10 , further comprising:
a second sidewall spacer layer extending upwardly along outer sidewalls of first sidewall spacer layer; and
an inter-layer dielectric layer disposed along outer sidewalls of the second sidewall spacer layer and extending upward to upper surfaces of the first and second sidewall spacer layers.

12. The integrated circuit device of claim 10 , wherein the first ferromagnetic layer is a free layer configured to switch between at least two different magnetic orientations, and the second ferromagnetic layer is a pinned layer having a fixed magnetic orientation.

13. The integrated circuit device of claim 10 , wherein at least one of the first ferromagnetic layer and the second ferromagnetic layer are made of NiFe, CoFe, or CoFeB.

14. The integrated circuit device of claim 10 , wherein the substantially aligned sidewalls of the insulating barrier layer and the second ferromagnetic layer are spaced apart from sidewalls of the first ferromagnetic layer.

15. An integrated circuit device, comprising:
a substrate;
a lower NiFe, CoFe, or CoFeB layer arranged over an upper surface of the substrate;
an metal oxide layer arranged over the lower NiFe, CoFe, or CoFeB layer;
an upper NiFe, CoFe, or CoFeB layer arranged over the metal oxide layer, wherein the upper NiFe, CoFe, or CoFeB layer and the metal oxide layer have substantially aligned sidewalls; and
a first set of spacers resting on upper outer edges of the lower NiFe, CoFe, or CoFeB layer, and extending upwardly along the substantially aligned sidewalls of the metal oxide layer and the upper NiFe, CoFe, or CoFeB layer.

16. The integrated circuit device of claim 15 , wherein the lower NiFe, CoFe, or CoFeB layer is configured to switch between at least two different magnetic orientations and the upper NiFe, CoFe, or CoFeB layer has a fixed magnetic orientation.

17. The integrated circuit device of claim 15 , further comprising:
a bottom electrode arranged between the lower NiFe, CoFe, or CoFeB layer and the substrate, wherein the bottom electrode has a first width as measured between its outer sidewalls which is greater than a second width as measured between the substantially aligned sidewalls.

18. The integrated circuit device of claim 17 , further comprising:
a second set of spacers resting on upper outer edges of the bottom electrode, and extending upwardly along outer sidewalls of first set of spacers.

19. The integrated circuit device of claim 18 , further comprising:
an inter-layer dielectric layer disposed along outer sidewalls of the second set of spacers and extending upward to an upper surface of the second set of spacers.

20. The integrated circuit device of claim 15 :
wherein the upper NiFe, CoFe, or CoFeB layer and the metal oxide layer have first width measured between the substantially aligned sidewalls; and
wherein the lower NiFe, CoFe, or CoFeB layer has a second width measured between its outer sidewalls, wherein the second width is greater than the first width.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Wei-Hang
• Sung Fu-Ting
• Hsu Chern-Yow
• Liu Shih-Chang
• Tsai Chia-Shiung

Classifications

• H01L43/02

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic

• H10N50/85

  Materials of the active region · CPC title