Magnetic tunnel junction (MTJ) storage element and spin transfer torque magnetoresistive random access memory (STT-MRAM) cells having an MTJ

Patent metadata

Field	Value
Publication number	US-9368716-B2
Application number	US-36388609-A
Country	US
Kind code	B2
Filing date	Feb 2, 2009
Priority date	Feb 2, 2009
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A magnetic tunnel junction storage element for a spin transfer torque magnetoresistive random access memory (STT-MRAM) bit cell includes a bottom electrode layer, a pinned layer adjacent to the bottom electrode layer, a dielectric layer encapsulating a portion of the bottom electrode layer and the pinned layer, the dielectric layer including sidewalls that define a hole adjacent to a portion of the pinned layer, a tunneling barrier adjacent to the pinned layer, a free layer adjacent to the tunneling barrier, and a top electrode adjacent to the free layer, wherein a width of the bottom electrode layer and/or the pinned barrier in a first direction is greater than a width of a contact area between the pinned layer and the tunneling barrier in the first direction. Also a method of forming an STT-MRAM bit cell.

First claim

What is claimed is:

1. A memory device having a magnetic tunnel junction (MTJ) storage element, the MTJ storage element comprising:
a bottom electrode;
a pinned layer adjacent to the bottom electrode;
a dielectric layer encapsulating a portion of the bottom electrode and the pinned layer, wherein the dielectric layer includes sidewalls that define a hole adjacent to a portion of the pinned layer;
a tunneling barrier adjacent to the pinned layer;
a free layer adjacent to the tunneling barrier, wherein a portion of one of the tunneling barrier or the free layer is disposed along the sidewall of the hole and perpendicular to substantially all of the bottom electrode and substantially all of the pinned layer; and
a top electrode adjacent to the free layer, wherein a width of the bottom electrode and/or the pinned layer in a first direction is greater than a width of a contact area between the pinned layer and the tunneling barrier in the first direction,
wherein the tunneling barrier is in contact with the sidewalls of the dielectric layer, and
wherein the free layer is not in contact with the sidewalls of the dielectric layer.

2. The memory device according to claim 1 , wherein the top electrode fills a portion of the hole over the free layer.

3. The memory device according to claim 1 ,
wherein the tunneling barrier has a U-shaped cross section with a first leg and a second leg, and
wherein the first leg extends along the sidewall of the hole.

4. The memory device according to claim 3 , wherein the free layer has a U-shaped cross section and is nested within the U-shaped cross section of the tunneling barrier.

5. The memory device according to claim 1 , wherein the memory device is applied in an electronic device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the memory device is integrated.

6. The memory device according to claim 1 , wherein the memory device is a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM).

7. The memory device according to claim 1 , wherein the pinned layer is substantially flat in the first direction.

8. The memory device according to claim 1 , wherein the pinned layer and the bottom electrode are substantially the same size in the first direction.

9. A memory device having a magnetic tunnel junction (MTJ) storage element, the MTJ storage element comprising:
bottom conductive means for electrically connecting the MTJ storage element;
first magnetic means for holding a first polarization, the first magnetic means being adjacent to the bottom conductive means;
first insulating means for encapsulating a portion of the bottom conductive means and the first magnetic means, wherein the first insulating means includes sidewalls that define a hole adjacent to a portion of the first magnetic means;
second magnetic means for holding a second polarization, wherein the second polarization is reversible;
second insulating means for tunneling current flowing between the first magnetic means and the second magnetic means, the second insulating means separating the first magnetic means and the second magnetic means, wherein a portion of one of the second insulating means or the second magnetic means is disposed along the sidewall of the hole and perpendicular to substantially all of the bottom conductive means and substantially all of the first magnetic means; and
top conductive means for electrically connecting the MTJ storage element, the top conductive means being adjacent to the second magnetic means, wherein a width of the bottom conductive means and/or the first magnetic means in a first direction is greater than a width of a contact area between the first magnetic means and the second insulating means in the first direction,
wherein the second insulating means is in contact with the sidewalls of the first insulating means, and
wherein the second magnetic means is not in contact with the sidewalls of the first insulating means.

10. The memory device according to claim 9 , wherein the top conductive means fills a portion of the hole over the second magnetic means.

11. The memory device according to claim 9 ,
wherein the second insulating means has a U-shaped cross section with a first leg and a second leg, and
wherein the first leg extends along the sidewall of the hole.

12. The memory device according to claim 11 , wherein the second magnetic means has a U-shaped cross section and is nested within the U-shaped cross section of the second insulating means.

13. The memory device according to claim 9 , wherein the memory device is applied in an electronic device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the memory device is integrated.

14. The memory device according to claim 9 , wherein the memory device is a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM).

15. A memory cell, comprising:
an interconnect; and
a magnetic tunnel junction (MTJ) storage element electrically coupled to the interconnect,
wherein the MTJ storage element comprises:
a bottom electrode above and in contact with the interconnect;
a pinned layer above and in contact with the bottom electrode;
a dielectric layer above the interconnect and encapsulating a portion of the bottom electrode and the pinned layer, wherein the dielectric layer includes sidewalls defining a hole above a portion of the pinned layer, and wherein a width of the hole is less than a width of the pinned layer;

a tunneling barrier within the hole and comprising:
a first tunneling barrier part above and in contact with the portion of the pinned layer exposed by the hole, and
a second tunneling barrier part adjacent to and in contact with the sidewalls of the dielectric layer;

a free layer within the hole and comprising:
a first free layer part over and in contact with the first tunneling barrier part, and
a second free layer part adjacent to and in contact with the second tunneling barrier part; and

a top electrode within the hole and in contact with the first free layer part and the second free layer part.

16. The memory cell according to claim 15 , wherein the bottom electrode and the interconnect are offset relative to each other such that a portion of the bottom electrode is not in contact with the interconnect and a portion of the interconnect is not in contact with the bottom electrode.

17. The memory cell according to claim 15 , wherein the free layer is not in contact with the sidewalls of the dielectric layer.

Assignees

• Gu Shiqun
• Kang Seung H
• Zhu Xiaochun
• Qualcomm Inc

Inventors

• Gu Shiqun
• Kang Seung H
• Zhu Xiaochun

Classifications

• H10D48/40

  Devices controlled by magnetic fields · CPC title

• H01L27/24

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L29/82

  Electricity · mapped topic