Method to etch non-volatile metal materials
US-2015340603-A1 · Nov 26, 2015 · US
Reversed stack MTJ
US9196825B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9196825-B2 |
| Application number | US-201314016343-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 3, 2013 |
| Priority date | Sep 3, 2013 |
| Publication date | Nov 24, 2015 |
| Grant date | Nov 24, 2015 |
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Abstract
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An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
First claim
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The invention claimed is: 1. An integrated circuit device, comprising: a substrate; a magnetic tunneling junction (MTJ) formed over a surface of the substrate, the MTJ comprising; a free layer configured to switch between at least two different magnetic orientations, arranged over the surface of the substrate; an insulating barrier layer arranged over the free layer; and a pinned layer having a fixed magnetic orientation, arranged over the insulating barrier layer, wherein…
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- What does patent US9196825B2 cover?
- An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter regi…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L43/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).