Fast detection of defective memory block to prevent neighbor plane disturb

Patent metadata

Field	Value
Publication number	US-10529435-B2
Application number	US-201815863404-A
Country	US
Kind code	B2
Filing date	Jan 5, 2018
Priority date	Jan 5, 2018
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.

First claim

We claim:

1. An apparatus, comprising:
memory cells in a first block, the memory cells in the first block are connected to a selected word line;
memory cells in a second block, the memory cells in the second block are connected to a selected word line; and
a control circuit, the control circuit configured to concurrently program the memory cells in the first block and the memory cells in the second block and to detect during the concurrent programming whether a defect exists in the second block, the control circuit to detect the defect is configured to:
subject the memory cells in the first block to a first verify test;
determine a reference program loop in which a predetermined number of the memory cells in the first block pass the first verify test;
subject the memory cells in the second block to the first verify test; and
determine whether a predetermined number of the memory cells in the second block pass the first verify test within a first number of program loops after the reference program loop.

2. The apparatus of claim 1 , further comprising:
a voltage source configured to provide a voltage signal which is shared by the selected word line of the first block and the selected word line of the second block during the concurrent programming, the voltage signal comprises a verify voltage of a lowest assigned programmed data state among a plurality of assigned programmed data states.

3. The apparatus of claim 2 , wherein:
the predetermined number of the memory cells in the first block are assigned to the lowest assigned programmed data state and comprise fastest-programming memory cells among memory cells in the first block which are assigned to the lowest assigned programmed data state.

4. The apparatus of claim 1 , wherein:
in response to detecting that the predetermined number of the memory cells pass the first verify test within the first number of program loops after the reference program loop, the control circuit is configured to make another detection during the concurrent programming of whether the defect exists in the second block; and
the control circuit to make the another detection is configured to:
subject the memory cells in the first block to a second verify test;
determine a second program loop in which the second verify test is passed by a predetermined number of the memory cells in the first block;
subject the memory cells in the second block to the second verify test; and
determine whether the second verify test is passed by a predetermined number of the memory cells in the second block within a specified number of additional program loops after the second program loop.

5. The apparatus of claim 4 , wherein:
the specified number of additional program loops is different than the second number of program loops.

6. The apparatus of claim 1 , wherein:
in response to the detection indicating that the first verify test is passed by the predetermined number of the memory cells in the second block within the first number of program loops, but not within a second number of program loops, after the reference program loop, where the second number is less than the first number, the control circuit is configured to make another detection during the concurrent programming of whether the defect exists in the second block; and
the control circuit to make the another detection is configured to:
subject the memory cells in the first block to a second verify test; and
determine a second program loop in which the second verify test is passed by a predetermined number of the memory cells in the first block;
subject memory cells in the second block to the second verify test; and
determine whether the second verify test is passed by a predetermined number of the memory cells in the second block within an additional number of program loops after the second program loop.

7. The apparatus of claim 1 , wherein:
in response to the detection indicating that the first verify test is passed by the predetermined number of the memory cells in the second block within the first number of program loops, but not within a second number of program loops, after the reference program loop, the control circuit is configured to make another detection during the concurrent programming of whether the defect exists in the second block; and
in response to the detection indicating that the first verify test is passed by the predetermined number of the memory cells in the second block within the first number of program loops and within the second number of program loops after the reference program loop, the control circuit is configured to complete the concurrent programming without another detection of whether the defect exists in the second block.

8. The apparatus of claim 1 , wherein:
in response to the detection indicating that the defect exists in the second block, the control circuit is configured to continue programming of the memory cells in the first block and to terminate programming of the memory cells in the second block.

9. The apparatus of claim 1 , further comprising:
a voltage source configured to provide a voltage signal which is shared by the selected word line of the first block and the selected word line of the second block during the concurrent programming; and
a switch between the second block and the voltage source, wherein the control circuit is configured to set the switch in a non-conductive state to block the voltage signal from reaching the second block, in response the detection indicating that the defect exists in the second block.

10. The apparatus of claim 1 , wherein:
the control circuit to determine the reference program loop, is configured to detect an upper tail of a threshold voltage distribution of the memory cells in the first block; and
the control circuit to determine whether the first verify test is passed by the predetermined number of the memory cells in the second block within the first number of program loops after the reference program loop, is configured to detect an upper tail of a threshold voltage distribution of the memory cells in the second block.

11. The apparatus of claim 1 , wherein:
the first number of program loops is a function of the reference program loop.

12. The apparatus of claim 1 , wherein:
the memory cells in the first block comprise memory cells with a first assigned programmed data state and memory cells with a second assigned programmed data state which is higher than the first assigned programmed data state;
the first verify test is for the first assigned programmed data state;
the predetermined number of the memory cells in the first block comprise memory cells with the second assigned programmed data state; and
during program voltages applied to the selected word line of the first block in the concurrent programming, the control circuit is configured to apply a slowdown measure for the memory cells with the first assigned programmed data state but not for the memory cells with the second assigned programmed data state before the detection is made, and to remove the slowdown measure for the memory cells with the first assigned programmed data state after the detection is made.

13. The apparatus of claim 12 , wherein:
to apply the slowdown measure, the control circuit is configured to apply a positive voltage to bit lines connected to the memory cells with the first assigned programmed data state; and
to remove the slowdown measure, the control circuit is configured to apply a ground voltage to the bit lines connected to the memory cells with the first assigned programmed data state.

14. The apparatus of claim 12 , wherein:
the control ci

Assignees

• Sandisk Technologies Llc

Inventors

• Puthenthermadam Sarath
• Dutta Deepanshu
• Pham Long

Classifications

• G11C2211/5622

  Concurrent multilevel programming of more than one cell · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C2211/5621

  Multilevel programming verification · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title