Apparatus and method for automatic bandwidth calibration for phase locked loop

Patent metadata

Field	Value
Publication number	US-9634826-B1
Application number	US-201514954819-A
Country	US
Kind code	B1
Filing date	Nov 30, 2015
Priority date	Nov 30, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.

First claim

We claim:

1. An apparatus comprising:
a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock;
a circuitry to apply a digital code to an output of the TDC; and
a node to receive the digital output code from the TDC and the digital code applied by the circuitry, wherein the circuitry is to monitor the digital output code and is to control the TDC according to at least the monitored digital output code.

2. The apparatus of claim 1 , wherein the digital code from the circuitry is a step signal, and wherein the circuitry is operable to apply the digital code by:
adding the digital code to the digital output code at the node, or
subtracting the digital code from the digital output code at the node.

3. The apparatus of claim 1 , wherein the circuitry is operable to adjust a first frequency to a second frequency, wherein the first and second frequencies indicate how often the circuitry is to switch the digital code from, being added to the digital output code at the node, to being subtracted from the digital output code at the node, and wherein the first frequency is lower than the second frequency.

4. The apparatus of claim 3 , wherein the first frequency is at most 2 MHz, and wherein the second frequency is at least 5 MHz.

5. The apparatus of claim 3 , wherein the circuitry is to apply, at the first frequency, the digital code, and wherein the circuitry is to then monitor an amplitude of the digital output code from the TDC to determine whether the amplitude is greater than a first threshold of an amplitude of the digital code applied by the circuitry.

6. The apparatus of claim 5 , wherein the circuitry is to control the TDC to cause the TDC to adjust its resolution when it is determined that the amplitude of the digital output code from the TDC is less than or equal to the first threshold of the amplitude of the digital code applied by the circuitry.

7. The apparatus of claim 6 , wherein the circuitry is to control the TDC to cause the TDC to adjust its resolution so long as the amplitude of the digital output code from the TDC is less than the first threshold of the amplitude of the digital code applied by the circuitry.

8. The apparatus of claim 5 , wherein the circuitry is to apply, at the second frequency, the digital code, and wherein the circuitry is to then monitor an amplitude of the digital output code from the TDC to determine whether the amplitude is greater than a second threshold of an amplitude of the digital code applied by the circuitry.

9. The apparatus of claim 8 , wherein the circuitry is to control the TDC to cause the TDC to adjust its resolution when it is determined that the amplitude of the digital output code from the TDC is greater than or equal to the second threshold of the digital code applied by the circuitry.

10. The apparatus of claim 9 , wherein the circuitry is to control the TDC to cause the TDC to adjust its resolution so long as the amplitude of the digital output code from the TDC is greater than the second threshold of the digital code applied by the circuitry.

11. The apparatus of claim 8 , wherein the first and second thresholds are programmable.

12. The apparatus of claim 8 , wherein the first and second thresholds are to be set at 0.7.

13. The apparatus of claim 1 comprises:
a digital loop filter (DLF) coupled to the TDC via the node;
an oscillator coupled to the DLF; and
a divider coupled to the oscillator, wherein the divider is to generate the feedback clock.

14. An apparatus comprising:
a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock;
a circuitry to apply a digital code to an output of the TDC;
a node to receive the digital output code from the TDC and the digital code from the circuitry; and
a digital loop filter (DLF) coupled to the TDC via the node, the DLF is to generate a filtered output, wherein the circuitry is to monitor the filtered output and is to control the TDC according to at least the monitored filtered output.

15. The apparatus of claim 14 , wherein the digital code from the circuitry is a step signal, and wherein the circuitry is operable to:
add the digital code to the digital output code at the node, or
subtract the digital code from the digital output code at the node.

16. The apparatus of claim 14 , wherein the circuitry is operable to adjust a first frequency to a second frequency, wherein the first and second frequencies indicate how often the circuitry is to switch the digital code from, being added to the digital output code at the node, to being subtracted from the digital output code at the node, and wherein the first frequency is lower than the second frequency.

17. The apparatus of claim 16 , wherein the first frequency is at most 2 MHz, and wherein the second frequency is at least 5 MHz.

18. The apparatus of claim 16 , wherein the circuitry is to apply, at the first frequency, the digital code, and wherein the circuitry is then operable to control a resolution of the TDC by monitoring a ratio of amplitudes of a triangular model representing the filtered output.

19. The apparatus of claim 18 , wherein the circuitry is to determine whether the ratio is less than a threshold, and is to cause the TDC to adjust its resolution when the ratio is greater than the threshold.

20. The apparatus of claim 16 , wherein the circuitry is to apply, at the second frequency, the digital code, and wherein the circuitry is then operable to control a resolution of the TDC by monitoring a ratio of amplitudes of a triangular model representing the filtered output.

21. The apparatus of claim 20 , wherein the circuitry is to determine whether the ratio is greater than a threshold, and is to cause the TDC to adjust its resolution when the ratio is less than the threshold.

22. A system comprising:
a memory;
a processor coupled to the memory, the processor having a phase locked loop (PLL) which includes:
a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock;
a digital loop filter (DLF) coupled to the TDC via the node;
an oscillator coupled to the DLF; and
a divider coupled to the oscillator, wherein the divider is to generate the feedback clock,

wherein the processor includes:
a circuitry to apply a digital code to an output of the TDC; and

a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code; and
a wireless interface for allowing the processor to communicate with another device.

23. The system of claim 22 , wherein the digital code from the circuitry is a step signal, and wherein the circuitry is operable to apply the digital code by:
adding the digital code to the digital output code at the node, or
subtracting the digital code from the digital output code at the node.

24. The system of claim 23 , wherein the circuitry is operable to adjust a first frequency to a second freq

Assignees

• Park Young Min
• Elzinga Mark
• Intel Corp

Inventors

• Park Young Min
• Elzinga Mark

Classifications

• H03M1/0607

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M1/0626 Primary

  by filtering · CPC title

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title