Phase-locked loop

Patent metadata

Field	Value
Publication number	US-10340928-B2
Application number	US-201815985563-A
Country	US
Kind code	B2
Filing date	May 21, 2018
Priority date	May 22, 2017
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

Systems and methods for providing improved linearity and reduced noise in a digital phase-locked loop in which a differential time-to-digital converter is implemented. Digital-to-time converters are used for adjusting a reference clock signal based on a fractional change signal and for adjusting a feedback signal based on another fractional change signal. Each fractional change signal is centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the fractional change signals can be described as (M+x) and (M−x), respectively. By implementing a differential time-to-digital converter, the sum of delays in each input path is kept constant so that integral non-linearity is improved. Supply sensitivity is also reduced, as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the delay range of a differential digital-to-time converter is half that of a single input digital-to-time converter.

First claim

What is claimed is:

1. A method comprising:
generating, by a clock module, a reference clock signal;
adjusting, by a first digital-to-time converter, the reference clock signal in accordance with a first control signal;
generating, by the first digital-to-time converter, a first input signal corresponding to the adjusted reference clock signal;
receiving, by a time-to-digital converter, the first input signal;
generating, by the time-to-digital converter, an output signal based on the first input signal;
generating an output high-frequency clock signal based on the output signal from the time-to-digital converter;
generating a derived signal from the output high-frequency clock signal;
adjusting, by a second digital-to-time converter, the derived signal in accordance with a second control signal, wherein a value of the first control signal and a value of the second control signal are centered about a midpoint value, M, and offset from the midpoint value by a fraction, x, such that the values of the first and second control signals are respectively defined as (M+x) and (M−x);
generating, by the second digital-to-time converter, a second input signal corresponding to the adjusted derived signal; and
receiving, by the time-to-digital converter, the second input signal, wherein the time-to-digital converter generates the output signal based on both the first input signal and the second input signal.

2. The method of claim 1 , wherein the derived signal comprises a feedback signal in a phase-locked loop architecture.

3. The method of claim 2 , further comprising:
generating a third control signal; and
using the third control signal to generate the feedback signal.

4. The method of claim 1 , further comprising:
filtering the output signal from the time-to-digital converter to generate a filtered output signal, wherein generating the output high-frequency clock signal comprises using the filtered output signal to generate the output high-frequency clock signal.

5. The method of claim 1 , wherein the derived signal comprises a phase selector output signal in a phase selector architecture.

6. The method of claim 1 , wherein generating the derived signal comprises using a phase selector to select a phase signal of the output high-frequency clock signal as the derived signal.

7. The method of claim 6 , wherein adjusting the derived signal in accordance with the second control signal comprises adjusting the selected phase signal in accordance with the second control signal.

8. The method of claim 1 , wherein the derived signal comprises a sub-sampled output signal in a sub-sampler architecture.

9. The method of claim 1 , wherein generating the derived signal comprises:
inputting both the reference signal and the output high-frequency clock signal to a sampler; and
using the sampler to generate, as the derived signal, a sampled signal based on the reference signal and the output high-frequency clock signal.

10. The method of claim 9 , wherein adjusting the derived signal in accordance with the second control signal comprises adjusting the sampled signal in accordance with the second control signal.

11. A system comprising:
a first clock module configured to generate a reference clock signal;
a first digital-to-time converter configured to adjust the reference clock signal in accordance with a first control signal and to generate an adjusted reference clock output signal;
a time-to-digital converter configured to receive, as a first input signal, the adjusted reference clock output signal from the first digital-to-time converter;
a second clock module configured to generate an output high-frequency clock signal based on an output from the time-to-digital converter;
a feedback module configured to receive the output high-frequency clock signal and to generate a derived signal based on the output high-frequency clock signal;
a second digital-to-time converter configured to adjust the derived signal in accordance with a second control signal and to provide the adjusted derived signal, as a second input signal, to the time-to-digital converter; and
a control module configured to generate the first and second control signals, wherein a value of the first control signal and a value of the second control signal are centered about a midpoint value, M, and offset from the midpoint value by a fraction, x, such that the values of the first and second control signals are respectively defined as (M+x) and (M−x).

12. The system of claim 11 , wherein the feedback module comprises a feedback loop of a phase-locked loop architecture, and the derived signal comprises a feedback signal.

13. The system claim 12 , wherein the feedback loop comprises a fractional-N module configured for generating the feedback signal.

14. The system of claim 13 , wherein the control module is further configured to generate a third control signal, and wherein the third control signal is applied to the fractional-N module to generate the feedback signal.

15. The system of claim 11 , further comprising at least one filter configured to filter the output from the time-to-digital converter and to generate a filtered output signal, and wherein the second clock module is configured to use the filtered output signal to generate the output high-frequency clock signal.

16. The system of claim 11 , wherein the feedback module comprises a phase selector, wherein the phase selector includes a multi-phase divider configured to select a phase signal as the derived signal, and wherein the second digital-to-time converter is configured to adjust the selected phase signal in accordance with the second control signal.

17. The system of claim 11 , wherein the feedback module comprises a sub-sampler, wherein the sub-sampler includes a sampler configured to receive both the reference signal and the output high-frequency clock signal and to generate, as the derived signal, a sampled signal based on the reference signal and the output high-frequency clock signal, and wherein the second digital-to-time converter is configured to adjust the sampled signal in accordance with the second control signal.

18. The system of claim 11 , wherein the control module comprises a sigma-delta module.

Assignees

• Stichting Imec Nederland

Inventors

• Mateman Paul

Classifications

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/081 Primary

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/0992 Primary

  comprising a counter or a frequency divider · CPC title

• H04L1/205

  jitter monitoring · CPC title