Methods and apparatus for semiconductor package processing

Patent metadata

Field	Value
Publication number	US-10515927-B2
Application number	US-201715634012-A
Country	US
Kind code	B2
Filing date	Jun 27, 2017
Priority date	Apr 21, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A fan-out process using chemical mechanical planarization (CMP) reduces the step-height between a semiconductor die and the surrounding overmolding of a reconstituted wafer. The reconstituted wafer is formed by overmolding a back side of at least one die that is placed with an active side facing down. The reconstituted wafer is then oriented to expose the die and the active side. A polymer layer is then formed over the reconstituted wafer. A CMP process then removes a portion of the polymer layer until a certain thickness above the die surface is obtained, reducing the step-height between the polymer layer on top of the die surface and the polymer layer on the adjacent mold compound surface. The CMP process can also be performed after a subsequent redistribution layer is formed on the reconstituted wafer.

First claim

The invention claimed is:

1. A method of processing a semiconductor substrate, comprising:
overmolding a non-active side of at least one die to form a reconstituted wafer;
orienting the reconstituted wafer to expose a first side with at least one active side of the at least one die;
depositing a first layer of polymer-based material on the first side of the reconstituted wafer; and
planarizing the first layer of polymer-based material without exposing the active side of the at least one die.

2. The method of claim 1 , further comprising:
forming at least one via in the first layer of polymer-based material after planarizing the first layer of polymer-based material, the via electrically connecting with the at least one die and extending to a first surface of the first layer of polymer-based material.

3. The method of claim 1 , further comprising:
forming a first redistribution layer on the reconstituted wafer;
depositing a second layer of polymer-based material over the first redistribution layer; and
planarizing the second layer of polymer-based material formed on the first redistribution layer.

4. The method of claim 3 , further comprising:
forming a redistribution layer on the at least one active side with at least two lead outs with line and spacing of approximately greater than 0/0 μm to less than or equal to approximately 2/2 μm.

5. The method of claim 3 , further comprising:
forming at least one via in the second layer of polymer-based material after planarizing the second layer of polymer-based material, the via electrically connecting with the first redistribution layer and extending to a second surface of the second layer of polymer-based material.

6. The method of claim 1 , further comprising using a carrier on a second side of the reconstituted wafer to provide rigidity during subsequent processing.

7. The method of claim 1 , further comprising creating structures on the reconstituted wafer before depositing the first layer of polymer-based material on the reconstituted wafer.

8. The method of claim 1 , further comprising:
planarizing the first layer of polymer-based material using chemical-mechanical planarization.

9. The method of claim 1 , further comprising:
depositing at least one layer of polymer-based material on the reconstituted wafer using a spin coating process.

10. A method of processing a semiconductor substrate, comprising:
placing at least one die on a substrate surface with at least one active side of the at least one die towards the substrate surface;
overmolding at least one non-active side of the at least one die to form a reconstituted wafer;
curing the overmolding;
releasing the reconstituted wafer from the substrate surface and exposing a first side of the reconstituted wafer with the at least one active side of the at least one die;
spin coating a first polymer layer on the first side of the reconstituted wafer; and
chemical-mechanical planarizing the first polymer layer to reduce step-height distance in proximity of a transition point of the at least one die and an adjacent surface.

11. The method of claim 10 , further comprising:
reducing at least one step-height until the at least one step-height is approximately greater than 0 μm to less than or equal to approximately 1 μm.

12. The method of claim 10 , further comprising:
forming at least one via in the first polymer layer after chemical-mechanical planarizing the first polymer layer, the via electrically connecting with the at least one active side of the at least one die and extending to a first surface of the first polymer layer.

13. The method of claim 10 , further comprising:
forming a first redistribution layer on the reconstituted wafer;
spin coating a second polymer layer over the first redistribution layer; and
chemical-mechanical planarizing the second polymer layer formed on the first redistribution layer.

14. The method of claim 13 , further comprising:
forming a redistribution layer on the at least one active side with at least two lead outs with line and spacing of approximately greater than 0/0 μm to less than or equal to approximately 2/2 μm.

15. The method of claim 13 , further comprising:
forming at least one via in the second polymer layer after chemical-mechanical planarizing the second polymer layer, the via electrically connecting with the first redistribution layer and extending to a second surface of the second polymer layer.

16. The method of claim 10 , further comprising using a carrier on a second side of the reconstituted wafer to provide rigidity during processing.

17. The method of claim 10 , further comprising creating structures on the reconstituted wafer before depositing the first polymer layer on the reconstituted wafer.

Assignees

• Applied Materials Inc

Inventors

• Lianto Prayudi
• See Guan Huei
• Sundarrajan Arvind
• Arnepalli Ranga Rao
• Goradia Prerna

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/09 Primary

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H01L21/02282

  Electricity · mapped topic

• H01L2224/95001

  Electricity · mapped topic