Semiconductor device

Patent metadata

Field	Value
Publication number	US-10515890-B2
Application number	US-201715817267-A
Country	US
Kind code	B2
Filing date	Nov 19, 2017
Priority date	Dec 28, 2016
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A semiconductor device which provides improved reliability. The semiconductor device includes: a wiring substrate having a first surface and a second surface opposite to the first surface; a chip condenser built in the wiring substrate, having a first electrode and a second electrode; a first terminal and a second terminal disposed on the first surface; and a third terminal disposed on the second surface. The semiconductor device further includes: a first conduction path for coupling the first terminal and the third terminal; a second conduction path for coupling the first terminal and the first electrode; a third conduction path for coupling the third terminal and the first electrode; and a fourth conduction path for coupling the second terminal and the first electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a wiring substrate having a first surface and a second surface opposite to the first surface;
a semiconductor chip having a first chip electrode and a second chip electrode and being mounted over the wiring substrate;
a chip condenser built in the wiring substrate, having a first electrode and a second electrode;
a first terminal and a second terminal disposed on the first surface;
a third terminal disposed on the second surface;
a first conduction path for coupling the first terminal and the third terminal;
a second conduction path for coupling the first terminal and the first electrode including a first via electrode coupled to the first electrode;
a third conduction path for coupling the third terminal and the first electrode; and
a fourth conduction path for coupling the second terminal and the first electrode including a second via electrode coupled to the first electrode,
wherein the fourth conduction path is coupled to the first electrode electrically independently from the first conduction path, the second conduction path, and the third conduction path, and
wherein in plan view, the chip condenser has a rectangular shape having a first long side, a second long side, a first short side, and a second short side and the first electrode is formed along the first short side.

2. The semiconductor device according to claim 1 ,
wherein the first via electrode and the second via electrode are arranged in parallel to the first long side in plan view.

3. The semiconductor device according to claim 1 ,
wherein in plan view, the first via electrode and the second via electrode are arranged along the first long side and the first via electrode is nearer to the first long side than the second via electrode and the second via electrode is nearer to the second long side than the first via electrode.

4. The semiconductor device according to claim 1 , further comprising:
a first bump electrode for coupling the first terminal and the first chip electrode; and
a second bump electrode for coupling the second terminal and the second chip electrode.

5. The semiconductor device according to claim 4 , further comprising:
a first insulating layer covering peripheries of the first bump electrode and the second bump electrode and filling between the first surface of the wiring surface and the semiconductor chip.

6. The semiconductor device according to claim 1 , further comprising:
a fourth terminal disposed on the second surface; and
a fifth conduction path for coupling the fourth terminal and the first electrode.

7. The semiconductor device according to claim 6 , further comprising:
a second insulating layer covering the second surface and having a first opening exposing the third terminal and a second opening exposing the fourth terminal,
wherein diameter of the second opening is smaller than diameter of the first opening.

8. The semiconductor device according to claim 1 , further comprising:
a third insulating layer covering the first surface and having a third opening exposing the first terminal, and a fourth opening exposing the second terminal,
wherein diameter of the third opening is equal to diameter of the fourth opening.

9. The semiconductor device according to claim 1 ,
the wiring substrate further comprising:
a fourth insulating layer having a third surface, a fourth surface opposite to the third surface, a first through hole, and a second through hole penetrating from the third surface to the fourth surface;
a first wiring covering the second through hole and being formed on the third surface;
a second wiring covering the second through hole and being formed on the fourth surface; and
a through-hole wiring being formed in the second through hole and coupled to the first wiring and the second wiring,
wherein the chip condenser has an upper surface and a lower surface opposite to the upper surface,
wherein the first electrode includes an upper electrode formed on the upper surface and a lower electrode formed on the lower surface, and
wherein in sectional view, thickness of the chip condenser including the upper electrode and the lower electrode is smaller than thickness of the fourth insulating layer including the first wiring and the second wiring.

10. The semiconductor device according to claim 9 , further comprising:
a fifth insulating layer covering the first wiring and the upper electrode,
wherein the fourth insulating layer and the fifth insulating layer are resin layers containing glass fiber.

11. The semiconductor device according to claim 10 , further comprising:
a third wiring formed over the fifth insulating layer; and
a sixth insulating layer covering the third wiring,
wherein the sixth insulating layer is made of epoxy resin.

12. A semiconductor device comprising:
a wiring substrate having a first surface and a second surface opposite to the first surface;
a semiconductor chip having a first chip electrode and a second chip electrode and being mounted over the wiring substrate;
a chip condenser built in the wiring substrate, having a first electrode and a second electrode;
a first terminal, a second terminal, a third terminal, and a fourth terminal disposed on the first surface;
a fifth terminal and a sixth terminal disposed on the second surface;
a first conduction path for coupling the first terminal and the fifth terminal;
a second conduction path for coupling the first terminal and the first electrode;
a third conduction path for coupling the fifth terminal and the first electrode; and
a fourth conduction path for coupling the second terminal and the first electrode;
a fifth conduction path for coupling the third terminal and the sixth terminal;
a sixth conduction path for coupling the third terminal and the second electrode;
a seventh conduction path for coupling the sixth terminal and the second electrode; and
an eighth conduction path for coupling the fourth terminal and the second electrode,
wherein the fourth conduction path is coupled to the first electrode independently from the first conduction path, the second conduction path, and the third conduction path, and
wherein the eighth conduction path is coupled to the second electrode independently from the fifth conduction path, the sixth conduction path, and the seventh conduction path.

13. The semiconductor device according to claim 12 , further comprising:
a first bump electrode for coupling the second terminal and the first chip electrode; and
a second bump electrode for coupling the fourth terminal and the second chip electrode.

14. The semiconductor device according to claim 13 , wherein the first bump electrode and the second bump electrode are located adjacent to each other without another bump electrode between them.

15. The semiconductor device according to claim 14 , further comprising:
a first solder ball electrode coupled to the fifth terminal; and
a second solder ball electrode coupled to the sixth terminal.

16. The semiconductor device according to claim 12 , further comprising:
a first conductive plate coupled to the fourth conduction path;
a second conductive plate coupled to the eighth conduction path; and
an insulating film located between the first conductive plate and the second conductive plate,
wherein the first conductive plate and the second conductive plate have a region where they overlap each other in plan view.

17. A semiconductor device comprising:
a wiring substrate having a first front surface where a plurality of first exter

Assignees

• Renesas Electronics Corp

Inventors

• Sato Yoshiaki
• Kariyazaki Shuuichi
• Nakagawa Kazuyuki

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/354

  comprising polymers · CPC title

• H10W72/325

  Die-attach connectors having a filler embedded in a matrix · CPC title