Substrate comprising an embedded capacitor

Patent metadata

Field	Value
Publication number	US-2016183379-A1
Application number	US-201414579735-A
Country	US
Kind code	A1
Filing date	Dec 22, 2014
Priority date	Dec 22, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a base portion, a first terminal and a second terminal. The first terminal is located on a first surface of the base portion, where the first terminal is the only terminal on the first surface of the base portion. The second terminal is located on a second surface of the base portion. The second surface is opposite to the first surface. The second terminal is the only terminal on the second surface of the base portion. In some implementations, the capacitor further includes a first base metal layer located between the first surface of the base portion and the first terminal. In some implementations, the capacitor also includes a second base metal layer located between the second surface of the base portion and the second terminal.

First claim

1 . A substrate comprising:
a first dielectric layer; and a capacitor embedded in the first dielectric layer, the capacitor comprising:
a base portion;
a first terminal located on a first surface of the base portion, wherein the first terminal is the only terminal on the first surface of the base portion; and
a second terminal located on a second surface of the base portion, the second surface opposite to the first surface, wherein the second terminal is the only terminal on the second surface of the base portion.

2 . The substrate of claim 1 , wherein the capacitor further comprises:
a first base metal layer located between the first surface of the base portion and the first terminal; and a second base metal layer located between the second surface of the base portion and the second terminal.

3 . The substrate of claim 1 , further comprising:
a first terminal interconnect coupled to the first terminal of the capacitor; and a second terminal interconnect coupled to the second terminal of the capacitor.

4 . The substrate of claim 3 , wherein the first terminal interconnect is coupled to the first terminal such that a substantial part of a horizontal portion of the first terminal is in contact with the first terminal interconnect.

5 . The substrate of claim 4 , wherein the second terminal interconnect is coupled to the second terminal such that a substantial part of a horizontal portion of the second terminal is in contact with the second terminal interconnect.

6 . The substrate of claim 3 , wherein the first terminal interconnect is coupled to the first terminal such that a majority of a horizontal portion of the first terminal is in contact with the first terminal interconnect.

7 . The substrate of claim 1 , wherein the capacitor comprises a lateral dimension of about 0.5 millimeter (mm) or less and/or a vertical dimension of about 0.1 millimeter (mm) or less.

8 . The substrate of claim 1 further comprising a core layer, the core layer comprising a cavity in which the capacitor is located in, the first dielectric layer formed in the substrate such that the first dielectric layer fills the cavity of the core layer and encapsulates the capacitor.

9 . The substrate of claim 8 , wherein the core layer comprises a first thickness, and the capacitor comprises a second thickness that is about the same or less than the first thickness.

10 . The substrate of claim 1 , wherein the substrate includes one of at least a package substrate and/or an interposer.

11 . The substrate of claim 1 , wherein the substrate is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

12 . A method for fabricating a substrate, comprising:
forming a first dielectric layer; and embedding a capacitor in the first dielectric layer, wherein embedding the capacitor comprises:
forming a base portion;
forming a first terminal on a first surface of the base portion, wherein the first terminal is the only terminal on the first surface of the base portion;
forming a second terminal on a second surface of the base portion, the second surface opposite to the first surface, wherein the second terminal is the only terminal on the second surface of the base portion; and
positioning the base portion, the first terminal, and the second terminal in the first dielectric layer.

13 . The method of claim 12 , wherein embedding the capacitor further comprises:
forming a first base metal layer between the first surface of the base portion and the first terminal; and forming a second base metal layer between the second surface of the base portion and the second terminal.

14 . The method of claim 12 , further comprising:
forming a first terminal interconnect on the first terminal of the capacitor; and forming a second terminal interconnect on the second terminal of the capacitor.

15 . The method of claim 14 , wherein the first terminal interconnect is coupled to the first terminal such that a substantial part of a horizontal portion of the first terminal is in contact with the first terminal interconnect.

16 . The method of claim 14 , wherein the first terminal interconnect is coupled to the first terminal such that a majority of a horizontal portion of the first terminal is in contact with the first terminal interconnect.

17 . The method of claim 12 , wherein the capacitor comprises a lateral dimension of about 0.5 millimeter (mm) or less and/or a vertical dimension of about 0.1 millimeter (mm) or less.

18 . The method of claim 12 , further comprising forming a core layer, the core layer comprising a cavity in which the capacitor is located in, the first dielectric layer formed in the substrate such that the first dielectric layer fills the cavity of the core layer and encapsulates the capacitor.

19 . The method of claim 19 , wherein the core layer comprises a first thickness, and the capacitor comprises a second thickness that is about the same or less than the first thickness.

20 . The method of claim 12 , wherein the substrate is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

Assignees

• Qualcomm Inc

Inventors

• Song Young Kyu
• We Hong Bok
• Hwang Kyu-Pyung

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H01G4/33

  Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

• H01G4/224

  Housing; Encapsulation · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/40

  Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title