Low permeability electrical feed-through

US10515668B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10515668-B2
Application numberUS-201916449310-A
CountryUS
Kind codeB2
Filing dateJun 21, 2019
Priority dateAug 9, 2017
Publication dateDec 24, 2019
Grant dateDec 24, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A low permeability electrical feed-through involves a laminate structure having alternating conductive and insulating layers with a conductive through-hole positioned therethrough, by which a lower connector pad is electrically connected with an upper connector pad. Such a feed-through may be used at an interface between a hermetically-sealed internal environment, such as in a lighter-than-air gas filled data storage device, and the external environment. An insulating layer is positioned and configured such that an associated horizontal leak path can meet an allowable feed-through leak rate, while the collection of layers is configured such that an associated vertical leak path can meet the feed-through leak rate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing an electrical feed-through component, the method comprising: forming a first layer of conductive material over a first side of a copper clad laminate first insulator material and a second layer of conductive material over a second opposing side of said first insulator material; etching away a circular portion of said second layer of conductive material; forming a pre-impregnated glass-epoxy resin second insulator material over said second layer of conductive material and said second side of said first insulator material exposed through said circular portion of said second layer of conductive material; forming a third layer of conductive material over said second insulator material; forming a through-hole through each of said first layer of conductive material, said first insulator material, said second insulator material, and said third layer of conductive material; forming a fourth conductive material covering an inside of said through-hole; filling with a resin said through-hole inside of said fourth conductive material; forming a first electrical pad conductive material over said first layer of conductive material and a second electrical pad conductive material over said third layer of conductive material; and etching away a portion of said first electrical pad conductive material and said first layer of conductive material to form a first electrical connector pad and a portion of said second electrical pad conductive material and said third layer of conductive material and to form a second electrical connector pad; wherein said first electrical connector pad and said second electrical connector pad are electrically connected via said fourth conductive material. 2. The method of claim 1 , wherein: said forming second insulator material includes forming a second insulator material having an anisotropic gas leak rate and positioned within said electrical feed-through such that said leak rate is lesser in a vertical direction than in a horizontal direction. 3. The method of claim 2 , wherein: said forming said second insulator material includes forming said second insulator material with a thickness that is less than a thickness of said first insulator material, thereby configuring a longer horizontal diffusion path through said second insulator material in the horizontal direction than in the vertical direction. 4. The method of claim 1 , wherein: said forming said second insulator material includes forming a diffusion path in a vertical direction through said second insulator material and through said first insulator material that is limited by a radial distance between said second layer of conductive material and said fourth conductive material. 5. The method of claim 1 , wherein: said etching away said circular portion of said second layer of conductive material and said etching away said portions of said third layer of conductive material and said second electrical pad conductive material include forming a capacitance area in which said second layer of conductive material partially overlaps with said third layer of conductive material and a ratio of said capacitance area to a thickness of said second insulator material is less than 10, to moderate a capacitive effect of said capacitance area. 6. A system for sealing an interface between a hermetically-sealed environment of an electronic component and an external environment, the system comprising: means for limiting a diffusion path in a horizontal direction through an insulator layer of an electrical feed-through positioned at said interface. 7. The system of claim 6 , further comprising: means for limiting a diffusion path in a vertical direction through multiple insulator layers of said feed-through. 8. The system of claim 6 , further comprising: means for moderating a capacitive effect on high frequency electrical signals that transmit through a capacitance area within said feed-through.

Assignees

Inventors

Classifications

  • G11B33/148Primary

    Reducing friction, adhesion, drag · CPC title

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  • G11B5/4846Primary

    Constructional details of the electrical connection between arm and support · CPC title

  • Installations of cables or lines through walls, floors or ceilings, e.g. into buildings · CPC title

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What does patent US10515668B2 cover?
A low permeability electrical feed-through involves a laminate structure having alternating conductive and insulating layers with a conductive through-hole positioned therethrough, by which a lower connector pad is electrically connected with an upper connector pad. Such a feed-through may be used at an interface between a hermetically-sealed internal environment, such as in a lighter-than-air …
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification G11B33/148. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 24 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).