Photonic chip with an input wavelength filter

US10514499B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10514499-B2
Application numberUS-201815875559-A
CountryUS
Kind codeB2
Filing dateJan 19, 2018
Priority dateJan 19, 2018
Publication dateDec 24, 2019
Grant dateDec 24, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

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A photonic chip includes a device layer and a port layer, with an optical port located at the port layer. Inter-layer optical couplers are provided for coupling light between the device and port layers. The inter-layer couplers may be configured to couple signal light but block pump light or other undesired wavelength from entering the device layer, operating as an input filter. The port layer may accommodate other light pre-processing functions, such as optical power splitting, that are undesirable in the device layer.

First claim

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What is claimed is: 1. A photonics chip comprising: at least one port layer; a device layer disposed above or below the at least one port layer; an optical port disposed at the at least one port layer for connecting optically to an external optical system at a first wavelength the external optical system including a source of a second wavelength λ 2 ; wherein the at least one port layer comprises a first port waveguide in optical communication with the optical port; wherein the device layer comprises a first device waveguide in optical communication with the first port waveguide at the first wavelength λ 1 ; and, wherein the first device waveguide is substantially optically decoupled from the first port waveguide at the second wavelength λ 2 . 2. The photonics chip of claim 1 wherein the first device waveguide is transparent at the first wavelength λ 1 and is absorptive at the second wavelength λ 2 , and the first port waveguide is transparent at the first and second wavelengths λ 1 and λ 2 . 3. The photonics chip of claim 2 wherein the device layer comprises semiconductor material and the at least one port layer comprises dielectric material. 4. The photonics chip of claim 1 wherein the second wavelength is an optical pump wavelength for pumping an external optical amplifier. 5. The photonics chip of claim 1 further comprising a photonics device in optical communication with the first device waveguide. 6. The photonics chip of claim 1 further comprising an optical absorber coupled to the first port waveguide for absorbing the second wavelength. 7. The photonics chip of claim 1 wherein the first port waveguide and the first device waveguide are disposed to form a two-layer wavelength-selective coupler that is configured to transfer light of the first wavelength λ 1 between the first port waveguide and the first device waveguide while substantially preventing light of the second wavelengths λ 2 from being coupled into the first device waveguide from the first port waveguide. 8. The photonics chip of claim 7 wherein the two-layer wavelength-selective coupler comprises a section of the first device waveguide that extends directly over or under a section of the first port waveguide along a coupling length that is selected so that the first device waveguide and the first port waveguide are optically coupled at the first wavelength λ 1 and optically decoupled at the second wavelengths λ 2 . 9. The photonics chip of claim 7 wherein the two-layer wavelength-selective coupler is an adiabatic optical coupler formed of a section of the first device waveguide extending directly over or under a section of the first port waveguide, wherein at least one of the sections is tapered. 10. The photonics chip of claim 1 wherein the first port waveguide terminates at an edge of the photonic chip to form the optical port. 11. The photonics chip of claim 1 wherein one of the first device waveguide and the first port waveguide comprises a grating coupler configured to couple the device waveguide to the first port waveguide at the first wavelength. 12. The photonics chip of claim 1 wherein the device layer further comprises a second device waveguide disposed to be optically coupled with the first port waveguide at the first wavelength λ 1 or a third wavelength λ 3 while being optically decoupled from the first port waveguide at the second wavelength λ 2 . 13. The photonics chip of claim 1 wherein the at least one port layer further comprises a second port waveguide for connecting to the external optical system at the first wavelength λ 1 or a third wavelength λ 3 , and wherein the first device waveguide comprises a second coupling portion disposed to be optically coupled with the second port waveguide at the first wavelength λ 1 or third wavelength λ 3 while being optically decoupled from the first device waveguide at the second wavelength λ 2 . 14. The photonics chip of claim 1 wherein: the at least one port layer further comprises a second port waveguide and an optical splitter disposed to split light received from the optical port in power between the first port waveguide and the second port waveguide before coupling to the device layer, and the device layer further comprises a second device waveguide in optical communication with the second port waveguide at the first wavelength λ 1 . 15. The photonics chip of claim 3 wherein the device layer comprises a silicon layer, and wherein the at least one port layer comprises one of silicon nitride, silicon oxynitride, or silica. 16. A method for blocking a second wavelength from a device layer of a photonic chip that is configured to operate at a first wavelength, the method comprising: forming a port waveguide for connecting to an external system in a second layer of the photonic chip that is disposed over or under the device layer in a direction perpendicular to the device layer, the external system comprising a source of the second wavelengths; and, optically coupling the port waveguide to a device waveguide disposed in the device layer in a wavelength selective manner so that the device waveguide is optically coupled to the port waveguide at the first wavelength λ 1 but is substantially optically decoupled at the second wavelength λ 2 , so that the second wavelengths λ 2 received in the port waveguide remains in the port waveguide without being coupled into the device layer. 17. The method of claim 16 comprising configuring the port waveguide and the device waveguide to extend directly one over the other along a coupling length that is selected for coupling at the first wavelength and for blocking the second wavelength from coupling into the device layer. 18. The method of claim 16 comprising using an etch stop layer of the photonic chip as the second layer. 19. The method of claim 16 comprising providing an optical absorber optically coupled to the port waveguide. 20. The method of claim 16 comprising using a semiconductor layer of the chip as the device layer, and a dielectric layer of the chip as the second layer.

Assignees

Inventors

Classifications

  • Geodesic lenses or integrated gratings · CPC title

  • Three-dimensional structures · CPC title

  • forming wavelength selective elements, e.g. multiplexer, demultiplexer · CPC title

  • Coupling light guides with opto-electronic elements · CPC title

  • the intermediate optical elements being wavelength selective optical elements, e.g. variable wavelength optical modules or wavelength lockers (G02B6/4246 takes precedence) · CPC title

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What does patent US10514499B2 cover?
A photonic chip includes a device layer and a port layer, with an optical port located at the port layer. Inter-layer optical couplers are provided for coupling light between the device and port layers. The inter-layer couplers may be configured to couple signal light but block pump light or other undesired wavelength from entering the device layer, operating as an input filter. The port layer …
Who is the assignee on this patent?
Elenion Tech Llc
What technology area does this patent fall under?
Primary CPC classification G02B6/12002. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 24 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).