Induced thermal gradients

Patent metadata

Field	Value
Publication number	US-10514305-B2
Application number	US-201715499689-A
Country	US
Kind code	B2
Filing date	Apr 27, 2017
Priority date	Mar 31, 2011
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

First claim

What is claimed is:

1. A memory device comprising:
a mode register including one or more bits to indicate a thermal offset based at least in part on a thermal gradient across the memory device, the thermal gradient indicative of a temperature difference between a thermal sensor location and a second location on the memory device;
a thermal sensor at the thermal sensor location;
circuitry to receive a command from a controller to write a value to the one or more bits of the mode register to provide the thermal offset; and
a temperature compensated self-refresh (TCSR) circuit to perform self-refresh at a rate based at least in part on the thermal offset.

2. The memory device of claim 1 , wherein the one or more bits are to indicate the thermal offset of zero or more degrees.

3. The memory device of claim 1 , wherein the memory device is to provide the thermal sensor location to the controller.

4. The memory device of claim 1 , wherein the thermal sensor comprises a single thermal sensor on the memory device.

5. The memory device of claim 1 , wherein the one or more bits to indicate the thermal offset include two bits.

6. The memory device of claim 1 , wherein:
the TCSR circuit is to perform self-refresh for all channels based on the thermal offset.

7. The memory device of claim 1 , wherein the memory device comprises one or more Wide IO memory dice.

8. A memory controller comprising:
circuitry to detect a thermal gradient across a memory device, the thermal gradient indicative of a temperature difference between a thermal sensor location and a second location on the memory device, the memory device including a thermal sensor at the thermal sensor location; and
an I/O interface to program one or more register bits of the memory device to indicate a thermal offset based at least in part on the thermal gradient;
wherein a temperature compensated self-refresh (TCSR) circuit of the memory device is to perform self-refresh at a rate based at least in part on the thermal offset.

9. The memory controller of claim 8 , wherein the circuitry to detect the thermal gradient is to: determine a temperature difference between a thermal sensor on a logic die coupled with the memory device and a thermal sensor on the memory device.

10. The memory controller of claim 8 , wherein the I/O interface is to program the one or more register bits responsive to detection of a change in the thermal gradient.

11. The memory controller of claim 8 , wherein:
the circuitry is to determine a thermal sensor location on the memory device; and
wherein the circuitry is to detect the thermal gradient based on the thermal sensor location on the memory device.

12. The memory controller of claim 11 , further comprising:
a register to indicate the thermal sensor location on the memory device.

13. The memory controller of claim 8 , wherein the memory controller comprises a Wide IO memory controller.

14. A system comprising:
a memory device comprising:
a mode register including one or more bits to indicate a thermal offset based at least in part on a thermal gradient across the memory device, the thermal gradient indicative of a temperature difference between a thermal sensor location and a second location on the memory device,
a thermal sensor at the thermal sensor location,
circuitry to receive a command from a controller to write a value to the one or more bits of the mode register to provide the thermal offset, and
a temperature compensated self-refresh (TCSR) circuit to perform self-refresh at a rate based at least in part on the thermal offset; and

a logic die coupled with the memory device.

15. The system of claim 14 , wherein the one or more bits are to indicate the thermal offset of zero or more degrees.

16. The system of claim 14 , wherein the memory device is to provide the thermal sensor location to the controller.

17. The system of claim 14 , wherein the thermal sensor comprises a single thermal sensor on the memory device.

18. The system of claim 14 , wherein the one or more bits to indicate the thermal offset include two bits.

19. The system of claim 14 , wherein:
the TCSR circuit is to perform self-refresh for all channels based on the thermal offset.

20. The system of claim 14 , wherein the memory device comprises one or more Wide IO memory dice.

21. The system of claim 14 , wherein the logic die comprises one or more of a processor, a memory controller, and a system on a chip (SoC).

22. The system of claim 21 , wherein the processor comprises a graphics processing unit (GPU) or an application processor.

23. The system of claim 14 , further comprising one or more of a display and an antenna.

Assignees

• Intel Corp

Inventors

• Shoemaker Kenneth D

Classifications

• G01K3/08 Primary

  giving differences of values (using thermoelectric elements G01K7/02); giving differentiated values · CPC title

• G01K7/00 Primary

  Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat (giving results other than momentary value of temperature G01K3/00) {; Power supply therefor, e.g. using thermoelectric elements} · CPC title

• G06F1/3225

  of memory devices · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/206

  comprising thermal management · CPC title