Circuit package for connecting to an electro-photonic memory fabric
US-2024345316-A1 · Oct 17, 2024 · US
Dynamic memory performance throttling
US9104540B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104540-B2 |
| Application number | US-201113997977-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 23, 2011 |
| Priority date | Dec 23, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misalignment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.
First claim
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What is claimed is: 1. A memory device comprising: a memory stack including a plurality of coupled memory elements, the memory elements including a plurality of ranks, the plurality of ranks including a first rank and a second rank; and a logic device including a memory controller; wherein the memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank; and wherein upon…
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- What does patent US9104540B2 cover?
- Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read r…
- Who is the assignee on this patent?
- Toronyi Brian, Shoemaker Kenneth, Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification G11C7/04. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).