3DIC interconnect apparatus and method

Patent metadata

Field	Value
Publication number	US-10510729-B2
Application number	US-201816208660-A
Country	US
Kind code	B2
Filing date	Dec 4, 2018
Priority date	Dec 19, 2013
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

First claim

What is claimed is:

1. An apparatus comprising:
a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first metal lines formed in the plurality of first dielectric layers over the first substrate, a first surface of the plurality of first dielectric layers facing the first substrate;
a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second metal lines formed in the second dielectric layers over the second substrate;
a conductive element extending from a second surface of the first semiconductor chip to one of the plurality of second metal lines in the second semiconductor chip, the conductive element having a first portion extending through the first substrate, a second portion extending through the plurality of first dielectric layers, and a third portion extending into the plurality of second dielectric layers; and
a plurality of dielectric liners interposed between the conductive element and the first substrate, the plurality of dielectric liners not extending between the conductive element and the plurality of first dielectric layers, the conductive element contacting a portion of the first surface of the plurality of first dielectric layers, wherein the plurality of dielectric liners comprises a first liner and a second liner, wherein the second liner is interposed between the first liner and the first substrate, wherein the first liner is a spacer-shaped structure.

2. The apparatus of claim 1 , wherein the conductive element comprises a conductive plug and a barrier layer interposed between the conductive plug and the plurality of first dielectric layers.

3. The apparatus of claim 1 , wherein the conductive element contacts the first liner and the second liner.

4. The apparatus of claim 1 , wherein a distance between a surface of the first liner to a sidewall of the first substrate is a same distance as a distance between a surface of the second liner to a sidewall of the first substrate.

5. The apparatus of claim 1 , wherein the conductive element extends into a recess of a first metal line of the plurality of first metal lines.

6. The apparatus of claim 1 , wherein the second liner completely separates the first liner from the first substrate.

7. An apparatus comprising:
a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first metal lines formed in the plurality of first dielectric layers over the first substrate, a first surface of the plurality of first dielectric layers facing the first substrate;
a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second metal lines formed in the second dielectric layers over the second substrate;
a dielectric layer, wherein the first substrate is interposed between the dielectric layer and the plurality of first dielectric layers;
a conductive element extending from a second surface of the first semiconductor chip to one of the plurality of second metal lines in the second semiconductor chip, the conductive element having a first portion extending through the first substrate, a second portion extending through the plurality of first dielectric layers, and a third portion extending into the plurality of second dielectric layers; and
one or more dielectric liners interposed between the conductive element and the first substrate, the one or more dielectric liners comprising a first liner contacting the first substrate, wherein the conductive element contacts the first liner and the first surface of the plurality of first dielectric layers, wherein the first liner contacts a sidewall of the dielectric layer, wherein a surface of the dielectric layer, a surface of the first liner, and a surface of the conductive element are coplanar.

8. The apparatus of claim 7 , wherein the conductive element comprises a conductive plug and a conductive liner, wherein the conductive liner is interposed between the conductive plug and the first substrate.

9. The apparatus of claim 8 , wherein the conductive liner comprises Ta, TaN, TiN, Ti, or CoW.

10. The apparatus of claim 7 , wherein the conductive element extends into a recess of a first line of the plurality of first metal lines.

11. The apparatus of claim 7 , wherein the one or more dielectric liners comprise a second liner over the first liner, wherein the second liner completely separates the first liner from the first substrate.

12. The apparatus of claim 7 , wherein the one or more dielectric liners comprise a second liner over the first liner, wherein the second liner is a spacer-shaped structure.

13. An apparatus comprising:
a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first metal lines formed in the plurality of first dielectric layers over the first substrate, a first surface of the plurality of first dielectric layers facing the first substrate;
a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second metal lines formed in the second dielectric layers over the second substrate;
a conductive element extending from a second surface of the first semiconductor chip to one of the plurality of second metal lines in the second semiconductor chip, the conductive element having a first portion extending through the first substrate, a second portion extending through the plurality of first dielectric layers, and a third portion extending into the plurality of second dielectric layers; and
a plurality of dielectric liners interposed between the conductive element and the first substrate, the plurality of dielectric liners comprising a first liner contacting the first substrate and a second liner contacting the first liner, wherein the first liner completely separates the conductive element from the first surface of the plurality of first dielectric layers.

14. The apparatus of claim 13 , wherein the second liner is a spacer-shaped structure.

15. The apparatus of claim 13 , wherein the conductive element extends into a first metal line of the first plurality of metal lines.

16. The apparatus of claim 13 , wherein a width of the first portion is greater than a width of the second portion, and wherein a width of the second portion is greater than a width of the third portion.

17. The apparatus of claim 13 , wherein the third portion contacts a first surface of the one of the plurality of second metal lines, wherein the first surface of the one of the plurality of second metal lines faces the first substrate.

18. The apparatus of claim 13 , wherein the conductive element electrically couples the first semiconductor chip to the second semiconductor chip.

19. The apparatus of claim 13 , wherein the first liner extends away from a sidewall of the first substrate further than the second liner.

20. The apparatus of claim 13 , wherein a distance of a first surface of the second liner to the first surface of the plurality of first dielectric layers is equal to a distance of a first surface of the first liner to the first surfac

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Shu-Ting
• Yaung Dun-Nian
• Liu Jen-Cheng
• Chen U-Ting
• Chou Shih Pei

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title