Connecting through vias to devices

Patent metadata

Field	Value
Publication number	US-9355935-B2
Application number	US-201514841517-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 10, 2012
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Methods and devices for connecting a through via and a terminal of a transistor formed of a strained silicon material are provided. The terminal, which can be a source or a drain of a NMOS or a PMOS transistor, is formed within a substrate. A first contact within a first inter-layer dielectric (ILD) layer over the substrate is formed over and connected to the terminal. A through via extends through the first ILD layer into the substrate. A second contact is formed over and connected to the first contact and the through via within a second ILD layer and a contact etch stop layer (CESL). The second ILD layer is over the CESL, and the CESL is over the first ILD layer, which are all below a first inter-metal dielectric (IMD) layer and the first metal layer of the transistor.

First claim

What is claimed is:

1. A device comprising:
a transistor having a first source/drain region formed within a substrate, a second source/drain region formed within the substrate, and a gate structure overlying a channel region of the transistor, the channel region being between the first and second source/drain region;
a first contact over and electrically connected to the first source/drain region, the first contact being within a first dielectric layer over the substrate;
a through via extending through the first dielectric layer and into the substrate; and
a second contact over the first contact and over the through via, the second contact being connected to the first contact and the through via, the second contact extending through a second dielectric layer and a third dielectric layer, the second dielectric layer being on the first dielectric layer and the third dielectric layer being on the second dielectric layer, wherein the second contact extends over a shallow trench isolation feature.

2. The device of claim 1 , wherein the first dielectric layer is a first inter dielectric layer (ILD) and the third dielectric layer is a second ILD, and wherein the second dielectric layer is a contact etch stop layer (CESL).

3. The device of claim 1 , wherein the first source/drain region has a lattice constant that is different than a lattice constant of the substrate.

4. The device of claim 1 , wherein the first dielectric layer comprises a material selected from the group consisting of an oxide, SiO2, borophosphosilicate glass (BPSG), TEOS, spin-on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), high-density plasma (HDP) oxide, and plasma-enhanced TEOS (PETEOS).

5. The device of claim 1 , wherein the second dielectric layer imposes a strain upon the channel region.

6. The device of claim 1 , wherein the through via comprises a liner and a barrier layer, both the liner and the barrier layer extending around the through via and extending through the first dielectric layer into the substrate.

7. The device of claim 2 , wherein the first ILD layer and the second ILD layer comprise a material selected from a group consisting essentially of an oxide, SiO2, borophosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS), spin-on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), high-density plasma (HDP) oxide, or plasma-enhanced TEOS (PETEOS).

8. A device, comprising:
a substrate;
a transistor formed at least partly within the substrate, the transistor including a first source/drain region, a second source/drain region, and a gate formed on a top surface of the substrate;
a first dielectric layer on the top surface of the substrate, wherein the gate is at least partially embedded within the first dielectric layer;
a through via extending through the first dielectric layer and extending into the substrate, the through via including a conductive feature and a liner layer surrounding the conductive feature;
a contact embedded within a second dielectric layer overlying the first dielectric layer, the contact electrically contacting the first source/drain region and electrically contacting the through via; and

an etch stop layer between the top surface of the substrate and the first dielectric layer.

9. The device of claim 8 , wherein the etch stop layer imposes a strain upon a channel region of the transistor.

10. The device of claim 8 , wherein the contact extends through the etch stop layer.

11. The device of claim 8 , further comprising an isolation feature between the transistor and the through via.

12. The device of claim 11 , wherein the contact extends over the isolation feature.

13. The device of claim 8 , wherein the first source/drain region has a first lattice constant and the second source/drain region has the first lattice constant, and the substrate has a second lattice constant different than the first lattice constant.

14. The device of claim 8 , further comprising an interconnect structure formed over the transistor and the through via, the interconnect structure electrically contacting the gate and the second source/drain region.

15. The device of claim 8 , wherein the through via comprises:
a trench extending from a top surface of the first dielectric layer;
a liner lining the trench;
a barrier layer lining the liner; and
a conductor filling the trench.

16. A method comprising:
forming a first source/drain region in a substrate;
depositing an etch stop layer on the substrate;
depositing a first dielectric layer over the substrate and on the etch stop layer;
forming in the first dielectric layer a first contact electrically contacting the first source/drain region;
etching the first dielectric layer and the substrate to form a trench extending through the first dielectric layer and into the substrate;
filling the trench with a conductor;
depositing a second dielectric layer over the through via; and
forming in the second dielectric layer a second contact, the second contact electrically connecting the first contact and the conductor.

17. The method of claim 16 , wherein the step of forming a first source/drain region in a substrate includes:
forming a recess in the substrate; and
epitaxially growing a strain material in the recess.

18. A device comprising:
a transistor having a first source/drain region formed within a substrate, a second source/drain region formed within the substrate, and a gate structure overlying a channel region of the transistor, the channel region being between the first and second source/drain region;
a first contact over and electrically connected to the first source/drain region, the first contact being within a first dielectric layer over the substrate;
a through via extending through the first dielectric layer and into the substrate; and
a second contact over the first contact and over the through via, the second contact being connected to the first contact and the through via, the second contact extending through a second dielectric layer and a third dielectric layer, the second dielectric layer being on the first dielectric layer and the third dielectric layer being on the second dielectric layer, wherein the second dielectric layer imposes a strain upon the channel region.

19. The device of claim 18 , wherein the first source/drain region has a first lattice constant and the second source/drain region has the first lattice constant, and the substrate has a second lattice constant different than the first lattice constant.

20. The device of claim 18 , further comprising an interconnect structure formed over the transistor and the through via, the interconnect structure electrically contacting the gate and the second source/drain region.

Assignees

• Taiwan Semiconductor Mfg
• Taiwan Semiconductor Manufactruing Company Ltd

Inventors

• Chen Ming-Fa
• Wang Yu-Young
• Jan Sen-Bor

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title