Process and temperature insensitive linear circuit

Patent metadata

Field	Value
Publication number	US-10505509-B2
Application number	US-201715798471-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Oct 31, 2017
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A circuit includes a front end section configured to receive input current signals; a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.

First claim

What is claimed is:

1. A circuit comprising:
a front end section including a shunt-feedback inverter having a feedback structure comprising metal-oxide-semiconductor devices, the front end section configured to receive input current signals;
a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and
an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.

2. The circuit of claim 1 , wherein the programmable gain amplifier section includes a plurality of coarse programmable gain stages and a fine programmable gain stage.

3. The circuit of claim 2 , wherein each of the coarse programmable gain stages includes:
a fixed shorted inverter in parallel with a switchable-shorted inverter; and
a shunt peaking inductor coupled in series with the fixed shorted inverter.

4. The circuit of claim 2 , wherein the fine programmable gain stage includes a plurality of switchable-shorted inverters.

5. The circuit of claim 1 , wherein the output buffer section includes a driver inverter and a shorted inverter connected in series, wherein the driver inverter drives the shorted inverter.

6. The circuit of claim 1 , further comprising:
a single-to-differential converter coupled between the front end section and the programmable gain amplifier section and configured to provide differential signals to the programmable gain amplifier section, the single-to-differential converter including at least a first inverter and a second inverter, the first inverter having an input coupled to the front end section and an output coupled to an input of the second inverter, the second inverter having an output coupled to the programmable gain amplifier section, the input and the output of the second inverter being shorted.

7. The circuit of claim 6 , wherein the programmable gain amplifier section includes:
a first signal path having a first plurality of inverters connected in series without a resistor disposed therebetween, wherein the first signal path is coupled directly after the front end section; and
a second signal path having a second plurality of inverters connected in series without a resistor disposed therebetween, wherein the second signal path is coupled directly after the single-to-differential converter.

8. The circuit of claim 7 , wherein the first signal path and the second signal path are cross-coupled via inverters, thereby reducing amplitude and phase mismatches between signals of the first signal path and the second signal path.

9. The circuit of claim 6 , further comprising:
a first feedback circuit coupled between a current source of the circuit and the output of the second inverter of the single-to-differential converter; and
a second feedback circuit coupled between an output of the output buffer section and a first stage of the programmable gain amplifier section.

10. A device comprising:
a transimpedance amplifier; and
a programmable linear regulator configured to provide an adjustable voltage to the transimpedance amplifier;
wherein the transimpedance amplifier includes:
a front end section configured to receive input current signals;
a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and
an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.

11. The device of claim 10 , further comprising:
a ring oscillator coupled to an output of the programmable linear regulator; and
a frequency comparator coupled to the ring oscillator and configured to compare a frequency of the ring oscillator and a reference frequency,
wherein the programmable linear regulator is controlled based on a comparison result of the frequency comparator.

12. The device of claim 10 , wherein the front end section includes a shunt-feedback inverter having a feedback path that includes metal-oxide-semiconductor devices.

13. The device of claim 10 , wherein the programmable gain amplifier section includes a plurality of coarse programmable gain stages and a fine programmable gain stage.

14. The device of claim 13 , wherein each of the coarse programmable gain stages includes:
a fixed shorted inverter in parallel with a switchable-shorted inverter; and
a shunt peaking inductor coupled in series with the fixed shorted inverter.

15. The device of claim 13 , wherein the fine programmable gain stage includes a plurality of switchable-shorted inverters.

16. The device of claim 10 , wherein the output buffer section includes a driver inverter and a shorted inverter connected in series, wherein the driver inverter drives the shorted inverter.

17. The device of claim 10 , further comprising:
a single-to-differential converter coupled between the front end section and the programmable gain amplifier section and configured to provide differential signals to the programmable gain amplifier section, the single-to-differential converter including at least a first inverter and a second inverter, the first inverter having an input coupled to the front end section and an output coupled to an input of the second inverter, the second inverter having an output coupled to the programmable gain amplifier section, the input and the output of the second inverter being shorted.

18. The device of claim 17 , wherein the programmable gain amplifier section includes:
a first signal path having a first plurality of inverters connected in series without a resistor disposed therebetween, wherein the first signal path is coupled directly after the front end section; and
a second signal path having a second plurality of inverters connected in series without a resistor disposed therebetween, wherein the second signal path is coupled directly after the single-to-differential converter.

19. The device of claim 18 , wherein the first signal path and the second signal path are cross-coupled via inverters, thereby reducing amplitude and phase mismatches between signals of the first signal path and the second signal path.

20. The device of claim 17 further comprising:
a first feedback circuit coupled between a current source of the transimpedance amplifier and the output of the second inverter of the single-to-differential converter; and
a second feedback circuit coupled between an output of the output buffer section and a first stage of the programmable gain amplifier section.

Assignees

• Cisco Tech Inc

Inventors

• Lakshmikumar Kadaba
• Kurylak Alexander Christopher
• Nagaraju Manohar
• Booth Richard Van Hoesen

Classifications

• H03G1/0088

  using discontinuously variable devices, e.g. switch-operated · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• H03F1/0233

  by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

• H03F1/30

  Modifications of amplifiers to reduce influence of variations of temperature or supply voltage {or other physical parameters (in differential amplifiers H03F3/45479)} · CPC title

• H03F2200/78

  A comparator being used in a controlling circuit of an amplifier · CPC title