Regulated cascode (RGC)-type burst mode optic pre-amplifier having extended linear input range

Patent metadata

Field	Value
Publication number	US-9762186-B2
Application number	US-201514887869-A
Country	US
Kind code	B2
Filing date	Oct 20, 2015
Priority date	Nov 14, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A Regulated Cascode (RGC)-type burst mode optic pre-amplifier having an extended linear input range. The burst mode optic pre-amplifier comprises an RGC-type Trans Impedance Amplifier (TIA), wherein a current path is added in the circuit of the RGC-type TIA to control a linearity state of the RGC-type TIA, and a main voltage gain is controlled in other circuit blocks after the RGC-type TIA.

First claim

What is claimed is:

1. A burst-mode optical pre-amplifier comprising:
a Regulated Cascode (RGC) type Trans-Impedance Amplifier (TIA),
wherein a current path is added in the circuit of the RGC-type TIA to control a linearity state of the RGC-type TIA, and a main voltage gain controlled in other circuit blocks after the RGC-type TIA; and wherein
the current path comprises a switch connected to an input node of the RGC-type TIA in parallel, and a current source connected to the input node of the RGC-type TIA in parallel and to the switch in serial; and
the current path extends a linear input range of the RGC-type TIA.

2. The burst mode optical pre-amplifier of claim 1 , wherein the current path further extends the linear input range of the RGC-type TIA by adjusting a current value of the current source.

3. The burst mode optical pre-amplifier of claim 1 , wherein the current path further extends the linear input range of the RGC-type TIA by providing a plurality of current sources arranged in parallel so as to adjust a gain in multiple steps.

4. The burst mode optical pre-amplifier of claim 1 , further comprising:
a TIA configured to convert a received current signal into a voltage signal and amplify the voltage signal;
a Single to Differential (S2D) amplifier configured to converts the voltage signal from the TIA into a first differential signal and amplify the first differential signal;
an Auto Offset Cancellation (AOC) amplifier provided appropriate amplification of a second differential signal without waveform distortion by removing a DC-offset in the second differential signal;
a buffer amplifier configured to output a final differential output signal by receiving and amplifying the second differential signal;
a peak detector configured to provide a discrimination value by detecting a level of a peak value of the voltage signal received from the TIA; and
a digital controller configured to provide a first control voltage signal to the S2D amplifier and the buffer amplifier and a second control voltage signal to the TIA by receiving the discrimination value from the peak detector,
wherein the first control voltage signal is for controlling a voltage gain of the S2D amplifier and the buffer amplifier, and the second control voltage signal is for distributing an input current of a RGC core circuit so as to extend the linear input range of the RGC-type TIA.

5. The burst mode optical pre-amplifier of claim 4 , wherein, once a loud burst packet signal is applied, the TIA turns on the switch by causing the digital controller to output the second control voltage and distributes a loud input current to the current source connected to the switch so as to be extended the linear input range of the RGC-type TIA.

6. The burst mode optical pre-amplifier of claim 4 ,
wherein the RGC-type TIA comprises:
a first current source supply transistor configured in a manner in which a source is connected to a first ground voltage, a drain is connected to the input node, and a bias voltage is applied to a gate;
a first NMOS transistor configured in a manner in which a source is connected to the input node, a drain is connected to a first resistor, and a gate is connected to an output node of a RGC feedback amplifier,
wherein the RGC feedback amplifier comprises: a second NMOS transistor configured in a manner in which a drain is connected to a second resistor as an output node of the RGC feedback amplifier, a source is connected to a second ground voltage, and a gate is connected to an input node of the RGC amplifier; and the second resistor formed between the output node of the RGC feedback amplifier and a second power voltage; and

the first resistor connected between the drain of the first NMOS transistor and a first power voltage,

wherein an output voltage is output through an output node between the first resistor and the first NMOS transistor.

7. The burst mode optical pre-amplifier of claim 4 , wherein the S2D amplifier comprises:
a gain controller configured to receive the first control voltage signal from the digital controller and adjusts a gain of the S2D amplifier in accordance with a source degeneration resistance value; and
a phase calibrator configured to calibrate a phase difference symmetrically between output differential signals.

8. The burst mode optical pre-amplifier of claim 7 , wherein the gain controller comprises:
a first transistor configured in a manner in which a source is connected to a ground voltage, a drain is connected to a third transistor, and a bias voltage is input to a gate;
a second transistor configured in a manner in which a source is connected to the ground voltage, a drain is connected to a fourth transistor, and the bias voltage is input to a gate;
the third transistor configured in a manner in which a source is connected to the first transistor, a drain is connected to a first resistor, and an output voltage of the TIA is input to a gate;
the fourth transistor configured in a manner in which a source is connected to the second transistor, a drain is connected to a second resistor, and an output voltage of a dummy TIA to a gate;
a source degeneration resistor formed between the sources of the third transistor and the fourth transistor, and having a resistance value to be determined by the first control voltage;
the first resistor formed between a power voltage and the third transistor;
the second resistor formed between the power voltage and the fourth transistor;
a first output node formed between the third transistor and the first resistor and configured to output a first negative signal; and
a second output node formed between the fourth transistor and the second resistor and configured to output a first positive signal.

9. The burst mode optical pre-amplifier of claim 7 , wherein:
the gain controller comprises a fifth transistor formed between a first output node and a second output node and a first capacitor formed between a switch connected to the first output node and a power voltage;
the switch connected to the first output node is controlled by the first control voltage signal which is the same as a voltage that controls the source degeneration resistor and the gate of the fifth transistor, and the first capacitor compensate for a phase difference between a first negative signal and the first positive signal of the gain controller by delaying a phase of a value of the first negative signal as much as a phase of a voltage applied to the fourth transistor is delayed; and
the phase calibrator comprises:
a sixth transistor configured in a manner in which a source is connected to a ground voltage, a drain is connected to a source of an eighth transistor, and a bias voltage is input to a gate;
a seventh transistor configured in a manner in which a source is connected to the ground voltage, a drain is connected to a source of a ninth transistor, and the bias voltage is input to a gate;
the eighth transistor configured in a manner in which the source is connected to the drain of the sixth transistor, a drain is connected to a third resistor, and a gate is connected to the first output node;
the ninth transistor configured in a manner in which the source is connected to the drain of the seventh transistor and the drain of the sixth transistor, a drain is connected a fourth resistor, and a gate is connected to the second output node;
a tenth transistor configured in a manner in which a source is connected to the ground voltage, a drain is connected to a source of a twelfth transistor, the bias voltage is input to a gate;
an eleventh transistor configured in a manner in which the source is connected to the ground voltage, and the bias voltage is input to a gate;
the third re

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Kim Young Ho

Classifications

• H03F3/08

  controlled by light · CPC title

• H03F3/082 Primary

  with FET's (H03F3/085 takes precedence) · CPC title

• H03F2200/435

  A peak detection being used in a signal measuring circuit in a controlling circuit of an amplifier · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F3/45197

  Pl types (H03F3/45224, H03F3/45251 take precedence) · CPC title