Method and system for a narrowband, non-linear optoelectronic receiver

Patent metadata

Field	Value
Publication number	US-9819422-B2
Application number	US-201514957083-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	Oct 10, 2007
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Methods and systems for a narrowband, non-linear optoelectronic receiver are disclosed and may include amplifying a received signal, limiting a bandwidth of the received signal, and restoring the signal utilizing a level restorer, which may include a non-return to zero (NRZ) level restorer comprising two parallel inverters, with one being a feedback path for the other. The inverters may be single-ended or differential. A photogenerated signal may be amplified in the receiver utilizing a transimpedance amplifier and programmable gain amplifiers (PGAs). A received electrical signal may be amplified via PGAs. The bandwidth of the received signal may be limited utilizing one or more of: a low pass filter, a bandpass filter, a high pass filter, a differentiator, or a series capacitance on the chip. The signal may be received from a photodiode integrated on the chip, where the photodiode may be AC coupled to an amplifier for the amplifying.

First claim

What is claimed is:

1. A method for processing signals, the method comprising:
in a receiver on a chip,
amplifying a received signal utilizing a transimpedance amplifier and one or more variable gain amplifiers (VGAs);
limiting a bandwidth of said received signal utilizing a band pass filter; and
restoring said received signal utilizing a non-return to zero (NRZ) level restorer comprising a pulse-triggered bistable circuit, wherein said pulse-triggered bistable circuit comprises two parallel inverters, and wherein a first of said inverters comprises a feedback path for a second of said inverters.

2. The method according to claim 1 , comprising limiting the bandwidth to be centered around a frequency of 5 GHz.

3. The method according to claim 1 , wherein said chip comprises a complementary metal-oxide semiconductor (CMOS) chip.

4. The method according to claim 1 , wherein said inverters comprise single-ended inverters.

5. The method according to claim 1 , wherein said inverters comprise differential inverters.

6. The method according to claim 1 , comprising amplifying a received electrical signal via one or more VGAs.

7. The method according to claim 1 , comprising limiting said bandwidth of said received signal utilizing one or more of: a differentiator or a series capacitance on said chip.

8. The method according to claim 1 , comprising receiving said signal from a photodiode integrated on said chip.

9. The method according to claim 8 , wherein said photodiode is AC coupled to an amplifier for said amplifying.

10. A system for processing signals, the system comprising:
in a receiver on a chip, one or more circuits operable to amplify a received signal utilizing a transimpedance amplifier and one or more variable gain amplifiers (VGAs);
said one or more circuits comprise a band pass filter; and
said one or more circuits restore said received signal utilizing a Non-return to Zero (NRZ) level restorer comprising a pulse-triggered bistable circuit, wherein said pulse-triggered bistable circuit comprises two parallel inverters, and wherein a first of said inverters comprises a feedback path for a second of said inverters.

11. The system according to claim 10 , wherein said one or more circuits are operable to limit the bandwidth to be centered around a frequency of 5 GHz.

12. The system according to claim 10 , wherein said chip comprises a complementary metal-oxide semiconductor (CMOS) chip.

13. The system according to claim 10 , wherein said inverters comprise single-ended inverters.

14. The system according to claim 10 , wherein said inverters comprise differential inverters.

15. The system according to claim 10 , wherein said one or more circuits are enabled to amplify a received electrical signal via one or more VGAs.

16. The system according to claim 10 , wherein said one or more circuits are enabled to limit said bandwidth of said received signal utilizing one or more of: a differentiator or a series capacitance on said chip.

17. The system according to claim 10 , wherein said one or more circuits are enabled to receive said signal from a photodiode integrated on said chip.

18. A system for processing signals, the system comprising:
in a receiver on a chip, one or more circuits that are operable to:
receive an electrical signal;
AC couple the electrical signal to an amplifier;
amplify the AC coupled electrical signal utilizing a transimpedance amplifier and one or more variable gain amplifiers (VGAs);
limit a bandwidth of the amplified signals; and
restore said received signal utilizing a Non-return to Zero (NRZ) level restorer comprising a pulse-triggered bistable circuit, wherein said pulse-triggered bistable circuit comprises two parallel inverters, and wherein a first of said inverters comprises a feedback path for a second of said inverters.

Assignees

• Luxtera Inc

Inventors

• Guckenberger John Andrew

Classifications

• H04B10/60

  Receivers · CPC title

• H04B10/66

  Non-coherent receivers, e.g. using direct detection · CPC title

• H04B10/2575

  Radio-over-fibre, e.g. radio frequency signal modulated onto an optical carrier · CPC title

• H04B10/6972 Primary

  using passive filtering · CPC title

• H04B10/69

  Electrical arrangements in the receiver · CPC title