Systems, methods and devices for work placement on processor cores

Patent metadata

Field	Value
Publication number	US-10503542-B2
Application number	US-201816048570-A
Country	US
Kind code	B2
Filing date	Jul 30, 2018
Priority date	Dec 17, 2015
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

First claim

The invention claimed is:

1. A non-transitory computer-readable storage medium that stores instructions for execution by a processing resource to perform operations of a power control unit within a processor, the operations, when executed by the processing resource, to perform a method, the method comprising to:
report fewer processing cores to an operating system than are present within the processor;
assign a first identifier to a first processing core within the processor and a second identifier to a second processing core within the processor;
detect a migration trigger that indicates detection of an instruction that would use a broken arithmetic unit on a first core;
determine to sequester the first processing core from use by the operating system and migrate a thread from the first processing core to the second processing core;
transmit a sleep transition message to the first processing core and the second processing core, the sleep transition message requesting a transition to a low-power state, the low-power state causing the first processing core to save a first context in a first processor context storage;
copy the first context from the first processor context storage to an intermediate storage;
copy the first context from the intermediate storage to a second processor context storage;
assign the first identifier to the second processing core;
sequester the first processing core from use by the operating system;
transmit a wake-up transition message to the second processing core, the wake-up transition message requesting a transition to an active state, the transition causing the second processing core to resume the first context from the second processor context storage and the second processing core to resume the first context from the second processor context storage; and
run a diagnostic sequence on the sequestered first processing core.

2. The non-transitory computer-readable storage medium of claim 1 , wherein the intermediate storage is external to a processor die.

3. The non-transitory computer-readable storage medium of claim 1 , wherein the low-power state is a C6 processor power state.

4. The non-transitory computer-readable storage medium of claim 1 ,
wherein the method further comprises to transfer a peripheral context between a first core peripheral controller and a second core peripheral controller, the first core peripheral controller electrically coupled to the first processing core and the second core peripheral controller electrically coupled to the second processing core.

5. The non-transitory computer-readable storage medium of claim 4 , wherein the method further comprises to stop interrupt requests to the first core peripheral controller and the second core peripheral controller during migration and configured to restart interrupt requests after migration.

6. A non-transitory computer-readable storage medium that stores instructions for execution by a processing resource to perform operations of a processor with multiple cores, the operations, when executed by the processing resource, to perform a method, the method comprising to:
report fewer processing cores to an operating system than are present within the processor;
detect a migration trigger that indicates detection of a broken arithmetic unit on a first core;
transmit a migration signal to the first core and a second core;
transition the first core to a sleep state, including:
save a first core software context to a first core context storage; and
enter the first core into a sleep state in which the first core is quiesced and halted;

transition the second core to a sleep state, including:
enter the second core into a sleep state in which the second core is quiesced and halted;
transfer a core identity from the first core to the second core;
sequester the first core from use by the operating system;
transfer the first core software context from the first core software context storage to a second core software context storage; wherein transferring the first processor software context from the first core software context storage to a second core software context storage comprises:
copying the first core software context from the first core context storage and the second core software context from the second core context storage to an intermediate storage; and
copying the first core software context from the intermediate storage to the second core software context storage and the second core software context from the intermediate storage to the first core software context storage; and

transmit a resume signal to the second core;

transition the second core from the sleep state to an active state, including:
restore the first core software context to the second core from the second core software context storage; and

run a diagnostic sequence on the sequestered first processing core.

7. The non-transitory computer-readable storage medium of claim 6 , wherein:
transitioning the first core to a sleep state further comprises halting a first core peripheral controller responsible for the first core;
transitioning the second core to a sleep state further comprises halting a second core peripheral controller responsible for the second core; and
the method further comprises transferring a core peripheral controller software context and the core identity from the first core peripheral controller to the second core peripheral controller.

8. The non-transitory computer-readable storage medium of claim 6 , further comprising stopping a migration based on a timeout threshold exceeded while waiting on a response to the migration signal from the first core or the second core.

9. The non-transitory computer-readable storage medium of claim 6 , further comprising transmitting a request to an operating system to transition a processor core workload from the first core to the second core; and
receiving an instruction from the operating system to transition the processor core workload from the first core to the second core.

Assignees

• Intel Corp

Inventors

• Therien Guy
• Sotomayor Guy
• Biswas Arijit
• Powell Michael D
• Dehaemer Eric J

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F9/461

  Saving or restoring of program or task context · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title

• G06F9/4893

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title