Power efficient processor architecture

Patent metadata

Field	Value
Publication number	US-9864427-B2
Application number	US-201615134770-A
Country	US
Kind code	B2
Filing date	Apr 21, 2016
Priority date	Sep 6, 2011
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A mobile device comprising:
an apparatus;
a dynamic random access memory (DRAM) coupled to the apparatus;
a data storage, wherein the apparatus comprises:
a cryptographic accelerator;
a video accelerator;
a memory controller; and
a processor comprising:
a first plurality of cores;
a second plurality of cores, wherein the second plurality of cores heterogeneous to and having a lower power consumption than the first plurality of cores;
an interconnect to couple the first plurality of cores and the second plurality of cores and a shared cache memory coupled to at least the first plurality of cores; and
a logic to cause a core of the second plurality of cores to execute an operation, wherein based at least in part on a performance level of the core of the second plurality of cores, the logic is to cause an execution state of the core of the second plurality of cores to be transferred to a core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation, wherein the logic is to cause the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state, analyze a plurality of interrupts and if a majority of the plurality of interrupts are to be handled by the core of the first plurality of cores, not wake the core of the second plurality of cores in response to the interrupt and instead wake the core of the first plurality of cores.

2. The mobile device of claim 1 , wherein the logic is to cause the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to the interrupt when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.

3. The mobile device of claim 1 , wherein the logic is to provide a subset of an execution state of the core of the first plurality of cores to the core of the second plurality of cores in response to the interrupt.

4. The mobile device of claim 3 , wherein in response to a determination that the core of the second plurality of cores cannot handle at least one requested operation, the logic is to obtain the subset of the execution state from the core of the second plurality of cores and to merge the execution state subset with a remainder of the execution state of the core of the first plurality of cores stored in a temporary storage area.

5. The mobile device of claim 1 , wherein the video accelerator is to perform a task and to send the interrupt to the logic upon completion of the task.

6. The mobile device of claim 1 , wherein the processor comprises a multicore processor, the logic comprising:
a wakeup logic;
a state transfer logic;
an undefined handling logic; and
an interrupt history storage.

7. The mobile device of claim 1 , further comprising an interrupt controller to receive a plurality of interrupts and direct the plurality of interrupts to one or more cores of at least one of the first plurality of cores and the second plurality of cores.

8. The mobile device of claim 1 , wherein the mobile device comprises a smartphone.

9. The mobile device of claim 1 , wherein the mobile device comprises a tablet computer.

10. The mobile device of claim 1 , further comprising an audio device.

11. The mobile device of claim 1 , wherein the core of the first plurality of cores further comprises at least one cache memory.

12. A method comprising:
causing a core of a second plurality of cores of a processor of a mobile device to execute an operation, based at least in part on a performance level of the core of the second plurality of cores, the processor comprising a first plurality of cores, the second plurality of cores heterogeneous to and having a lower power consumption than the first plurality of cores, an interconnect to couple the first plurality of cores and the second plurality of cores and a shared cache memory coupled to at least the first plurality of cores;
causing an execution state of the core of the second plurality of cores to be transferred to a core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation;
causing the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state; and
causing the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to the interrupt when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.

13. The method of claim 12 , further comprising providing a subset of an execution state of the core of the first plurality of cores to the core of the second plurality of cores in response to the interrupt.

14. At least one non-transitory computer readable storage medium comprising instructions that when executed enable a system to:
cause a core of a second plurality of cores of a processor of a mobile device to execute an operation, based at least in part on a performance level of the core of the second plurality of cores, the processor comprising a first plurality of cores, the second plurality of cores heterogeneous to and having a lower power consumption than the first plurality of cores, an interconnect to couple the first plurality of cores and the second plurality of cores and a shared cache memory coupled to at least the first plurality of cores;
cause an execution state of the core of the second plurality of cores to be transferred to a core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation;
cause the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state; and
cause the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to the interrupt when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.

15. A system comprising:
a processor comprising:
a first plurality of cores;
a second plurality of cores, a core of the second plurality of cores having a lower power consumption when in operation than a core of the first plurality of cores;
an interconnect coupled to the first plurality of cores and coupled to the second plurality of cores; and
a shared cache memory coupled to at least the first plurality of cores;
wherein, based at least in part on a performance requirement, an execution state is to be transferred from the core of the second plurality of cores to the core of the first plurality of cores to enable the core of the first plurality of cores to execute an operation, wherein the processor further comprises logic to:
cause the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state; and
cause th

Assignees

• Intel Corp

Inventors

• Herdrich Andrew J
• Illikkal Rameshkumar G
• Iyer Ravishankar
• Srinivasan Sadagopan
• Moses Jaideep
• Makineni Srihari

Classifications

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• Y02B70/30

  Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level · CPC title

• H04W88/02

  Terminal devices · CPC title

• H04W52/028

  switching on or off only a part of the equipment circuit blocks · CPC title