Migrating threads between asymmetric cores in a multiple core processor

Patent metadata

Field	Value
Publication number	US-9727388-B2
Application number	US-201113995340-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores including a first core and a second core; and
a memory to store a core characteristics identifier, the core characteristics identifier comprising a first identifier and a second identifier, the first identifier indicating first characteristics associated with the first core and the second identifier indicating second characteristics associated with the second core,
wherein the processor is to periodically monitor the first characteristics and the second characteristics and update the core characteristics identifier based on the first characteristics or the second characteristics, and further the processor generates an interrupt, in response to the processor detecting that one or more threads scheduled for execution by the first core include at least one instruction that the first core is incapable of executing, to cause an operating system to migrate the one or more threads from the first core to the second core according to a migration policy of a plurality of migration policies determined to apply based on the core characteristics identifier.

2. The processor as recited in claim 1 , wherein the core characteristics identifier is modified by the processor in response to the processor detecting a change in the first characteristics or the second characteristics.

3. The processor as recited in claim 1 , wherein:
the processor provides the core characteristics identifier to the operating system in response to a read core characteristics instruction; and
the one or more threads are migrated from the first core to the second core based on the core characteristics identifier.

4. The processor of claim 1 , wherein the first core and the second core are asymmetric cores.

5. A method performed by a hardware processor, the method comprising:
identifying one or more threads scheduled for execution at the hardware processor, the hardware processor comprising a plurality of cores including a first core having a first identifier and a second core have a second identifier, the first identifier indicating first characteristics associated with the first core and the second identifier indicating second characteristics associated with the second core,
initiating execution of the one or more threads by the first core;
periodically monitoring the first characteristic and the second characteristic;
updating a core characteristics identifier that comprises the first identifier and the second identifier, based on the first characteristic or the second characteristic;
determining to apply a migration policy of a plurality of migration policies based on the core characteristics identifier; and
in response to determining to apply the migration policy, initiating migrating the one or more threads from the first core to the second core by generating an interrupt to be received by an interrupt service routine.

6. The method as recited in claim 5 , further comprising:
stopping execution of the one or more threads by the first core;
saving a state of the first core;
mapping the state of the first core to create a mapped state for the second core;
migrating the one or more threads from the first core to the second core; and
resuming execution of the one or more threads by the second core based on the mapped state.

7. The method as recited in claim 5 , further comprising:
determining whether to apply a second migration policy; and
in response to determining to apply the second migration policy, initiating migrating the one or more threads from the second core to the first core based on the second migration policy.

8. The method as recited in claim 7 , further comprising:
stopping execution of the one or more threads by the second core;
saving a second state of the second core;
mapping the second state of the second core to create a second mapped state for the first core;
migrating the one or more threads to the first core; and
resuming execution of the one or more threads by the first core based on the second mapped state.

9. The method as recited in claim 5 , wherein determining whether to apply the migration policy comprises:
detecting that a first thermal characteristic associated with the first core satisfies a thermal threshold; and
detecting that a second thermal characteristic associated with the second core does not satisfy the thermal threshold.

10. The method as recited in claim 5 , wherein determining whether to apply the migration policy comprises:
detecting that a first throughput characteristic associated with the first core does not satisfy a throughput threshold; and
detecting that a second throughput characteristic associated with the second core satisfies the throughput threshold.

11. The method as recited in claim 5 , wherein determining whether to apply the migration policy comprises:
detecting that a first operating frequency characteristic associated with the first core does not satisfy an operating frequency threshold; and
detecting that a second operating frequency characteristic associated with the second core satisfies the operating frequency threshold.

12. The method as recited in claim 5 , wherein determining whether to apply the migration policy comprises detecting that a first power usage characteristic associated with the first core is greater than a second power usage characteristic associated with the second core.

13. The method of claim 5 , wherein the first core and the second core are asymmetric cores.

14. The method as recited in claim 5 , wherein determining whether to apply the migration policy comprises detecting that a first instruction set that the first core is capable of executing does not include at least one particular instruction and a second instruction set that the second core is capable of executing includes the at least one particular instruction.

15. A system comprising:
a processor comprising a plurality of cores including a first core and a second core;
a first memory to store a core characteristics identifier, the core characteristics identifier comprising a first identifier and a second identifier, the first identifier indicating first characteristics associated with the first core and the second identifier indicating second characteristics associated with the second core; and
a second memory to store an operating system including an interrupt handler;
and the processor executing the interrupt handler is to migrate one or more threads from the first core to the second core, according to a migration policy of a plurality of migration policies determined to apply based on the core characteristics identifier, upon receipt of a processor generated interrupt, wherein the processor generated interrupt is generated in response to the processor detecting that the one or more threads scheduled for execution by the first core include at least one instruction that the first core is incapable of executing, wherein the processor is to periodically monitors the first characteristics and the second characteristics and update the core characteristics identifier based on the first characteristics or the second characteristics.

16. The system of claim 15 , wherein the first core and the second core are asymmetric cores.

Assignees

• Jahagirdar Sanjeev S
• George Varghese
• Sodhi Inder
• Intel Corp

Inventors

• Jahagirdar Sanjeev S
• George Varghese
• Sodhi Inder

Classifications

• G06F9/4856 Primary

  resumption being on a different machine, e.g. task migration, virtual machine migration (G06F9/5088 takes precedence) · CPC title

• G06F9/5083 Primary

  Techniques for rebalancing the load in a distributed system · CPC title

• G06F9/30003

  Arrangements for executing specific machine instructions · CPC title