Method of producing display panel board

US10497725B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10497725-B2
Application numberUS-201716078280-A
CountryUS
Kind codeB2
Filing dateFeb 17, 2017
Priority dateFeb 26, 2016
Publication dateDec 3, 2019
Grant dateDec 3, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method includes a conductive film forming process of forming a conductive film 51 covering a gate insulation film IS and a semiconductor film 42, the gate insulation film 45 covering a gate electrode 37G and a gate line 35G formed on a glass substrate 32 and the semiconductor film 42 formed on the gate insulation film 45 while overlapping the gate electrode 37G, a first etching process of etching the conductive film 51 and forming a source conductive film 46S connected to the semiconductor film 42 and a drain conductive film 46D connected to the semiconductor film 42, a resist forming process performed after the first etching process and forming a resist 53R covering the semiconductor film 42, the source conductive film 46S, and the drain conductive film 46D, and a second etching process performed after the resist forming process and performing etching for removing the conductive film 51 while using the resist 53R as a mask.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of producing a display panel board comprising: a conductive film forming process of forming a conductive film covering a gate insulation film and a semiconductor film, the gate insulation film covering a gate electrode and a gate line formed on a substrate and the semiconductor film formed on the gate insulation film while overlapping the gate electrode; a first etching process performed after the conductive film forming process and etching the conductive film and forming a source conductive film and a drain conductive film, the source conductive film including a source electrode connected to the semiconductor film and the drain conductive film including a drain electrode connected to the semiconductor film; a resist forming process performed after the first etching process and forming a resist covering the semiconductor film, the source conductive film, and the drain conductive film; and a second etching process performed after the resist forming process and performing etching for removing the conductive film while using the resist as a mask. 2. The method of producing a display panel board according to claim 1 , wherein in the resist forming process, the resist is formed so as not to be disposed on at least a part of an extending portion of a step portion formed on the gate insulation film, the part of the extending portion extending from the source conductive film to the drain conductive film. 3. The method of producing a display panel board according to claim 1 , wherein in the first etching process, the source conductive film and the drain conductive film include source conductive films and drain conductive films, and the source conductive films and the drain conductive films are formed and arranged in an extending direction of the gate line, and in the resist forming process, the resist is formed so as not to be disposed at least on a part of a source in-between extending portion of a step portion formed on the gate insulation film, the part of the source in-between extending portion extending from one to another of two adjacent source conductive films. 4. The method of producing a display panel board according to claim 1 , wherein in the first etching process, the source conductive film and the drain conductive film include source conductive films and drain conductive films, and the source conductive films and the drain conductive films are formed and arranged in an extending direction of the gate line, out of two of the source conductive films having the drain conductive film therebetween, one source conductive film disposed on an opposite side from another source conductive film connected to the drain conductive film via the semiconductor film is an opposite-side source conductive film, and in the resist forming process, the resist is formed so as not to be disposed at least on a part of an opposite-side extending portion of a step portion formed on the gate insulation film, the part of the opposite-side extending portion extending from the drain conductive film to the opposite-side source conductive film. 5. The method of producing a display panel board according to claim 1 , wherein in the resist forming process, the resist is formed in a shape following a shape of the source conductive film and the drain conductive film. 6. The method of producing a display panel board according to claim 1 , wherein in the resist forming process, the resist is formed to cover the gate insulation film. 7. The method of producing a display panel board according to claim 1 , wherein the gate electrode and the gate line include aluminum.

Assignees

Inventors

Classifications

  • of organic photoresist masks · CPC title

  • using masks for conductive or resistive materials · CPC title

  • Wiring, e.g. gate line, drain line · CPC title

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Electricity · mapped topic

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What does patent US10497725B2 cover?
A method includes a conductive film forming process of forming a conductive film 51 covering a gate insulation film IS and a semiconductor film 42, the gate insulation film 45 covering a gate electrode 37G and a gate line 35G formed on a glass substrate 32 and the semiconductor film 42 formed on the gate insulation film 45 while overlapping the gate electrode 37G, a first etching process of etc…
Who is the assignee on this patent?
Sharp Kk
What technology area does this patent fall under?
Primary CPC classification H01L27/1288. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 03 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).