Methods for semiconductor passivation by nitridation after oxide removal

Patent metadata

Field	Value
Publication number	US-10490475-B2
Application number	US-201615169430-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	Jun 3, 2015
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

In some embodiments, a semiconductor surface may be effectively passivated by nitridation, preferably using hydrazine, a hydrazine derivative, or a combination thereof. The surface may be the semiconductor surface of a transistor channel region. In some embodiments, native oxide is removed from the semiconductor surface and the surface is subsequently nitrided. In some other embodiments, a semiconductor surface oxide layer is formed at the semiconductor surface and the passivation is accomplished by forming a semiconductor oxynitride layer at the surface, with the nitridation contributing nitrogen to the surface oxide to form the oxynitride layer. The semiconductor oxide layer may be deposited by atomic layer deposition (ALD) and the nitridation may also be conducted as part of the ALD.

First claim

What is claimed is:

1. A method for integrated circuit fabrication comprising:
removing native oxide from a surface of a semiconductor substrate to form a pre-clean substrate surface;
subsequently passivating the surface by exposing the pre-cleaned substrate surface to at least one of hydrazine and a hydrazine derivative to nitride the pre-cleaned surface to convert the pre-cleaned surface into a nitride passivation layer before depositing material from an other chemical species on the pre-cleaned surface;
depositing an interface layer on the nitride passivation layer, wherein the interface layer comprises a metal oxide comprising silicon; and
depositing a high-κ gate dielectric layer on the interface layer.

2. The method of claim 1 , wherein passivating the surface comprises passivating a transistor channel region.

3. The method of claim 1 , wherein the high-κ gate dielectric layer comprises hafnium oxide.

4. The method of claim 1 , wherein the metal oxide is lanthanum silicon oxide.

5. The method of claim 1 , wherein removing native oxide comprises exposing the surface to HCl.

6. The method of claim 1 , wherein removing native oxide comprises exposing the surface to a liquid phase etchant followed by exposing the substrate to a gas phase etchant.

7. The method of claim 1 , wherein the surface of the semiconductor substrate comprises a high-mobility semiconductor.

8. The method of claim 7 , wherein the high-mobility semiconductor comprises germanium.

9. The method of claim 8 , wherein the high-mobility semiconductor comprises silicon germanium.

10. The method of claim 9 , wherein the silicon germanium comprises less than 50% germanium.

11. The method of claim 1 , wherein the surface of the semiconductor substrate is a silicon surface.

12. A method for integrated circuit fabrication comprising:
removing native oxide from a surface of a transistor channel region of a semiconductor substrate to form a pre-clean substrate surface; and
nitriding the surface by exposing the pre-clean substrate surface to a nitrogen precursor to convert the pre-cleaned surface into a passivation layer before depositing material from an other chemical species on the surface;
depositing an interface layer directly on the passivation layer, wherein the interface layer comprises a metal oxide comprising silicon; and
depositing a gate dielectric layer directly on the interface layer, wherein the gate dielectric layer is thicker than the interface layer.

13. The method of claim 12 , wherein the nitrogen precursor is selected from the group consisting of hydrazine, hydrazine derivatives, and combinations thereof.

14. The method of claim 12 , wherein the channel region comprises silicon.

15. The method of claim 14 , wherein the channel region comprises silicon and germanium.

16. The method of claim 12 , wherein depositing the interface layer comprises depositing a layer of lanthanum silicon oxide; and wherein depositing the dielectric layer comprises depositing a layer of hafnium oxide.

Assignees

• Asm Ip Holding Bv

Inventors

• Xie Qi
• Tang Fu
• Givens Michael
• Raisanen Petri
• Maes Jan Willem
• Jiang Xiaoqiang

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/6506

  Formation of intermediate materials · CPC title

• H10P14/6502

  of treatments performed before formation of the materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title