Wafer-level packaging for enhanced performance

Patent metadata

Field	Value
Publication number	US-10490471-B2
Application number	US-201815992639-A
Country	US
Kind code	B2
Filing date	May 30, 2018
Priority date	Jul 6, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.

First claim

What is claimed is:

1. A method comprising:
providing a precursor wafer that includes a silicon handle layer, a stop layer, a device layer, and a plurality of first bump structures, wherein:
the device layer has a plurality of input/output (I/O) contacts at a top surface of the device layer;
the plurality of first bump structures are formed over the device layer, wherein each of the plurality of first bump structures is electronically coupled to a corresponding I/O contact;
the stop layer resides underneath the device layer; and
the silicon handle layer resides underneath the stop layer, such that the stop layer separates the device layer from the silicon handle layer;

applying a first mold compound over the device layer to encapsulate each of the plurality of first bump structures;
removing substantially the silicon handle layer;
applying a second mold compound to an exposed surface from which the silicon handle layer was removed; and
thinning down the first mold compound to provide a mold wafer, wherein a portion of each of the plurality of first bump structures is exposed.

2. The method of claim 1 wherein removing substantially the silicon handle layer is provided by one of a group consisting of chemical mechanical grinding, wet etching, and dry etching.

3. The method of claim 1 wherein applying the first mold compound is provided by one of a group consisting of compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation.

4. The method of claim 1 wherein applying the second mold compound is provided by one of a group consisting of compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation.

5. The method of claim 1 wherein thinning down the first mold compound is provided by mechanical grinding.

6. The method of claim 1 further comprising forming a plurality of second bump structures over the first mold compound after the first mold compound is thinned down, wherein each of the plurality of second bump structures is in contact with a corresponding first bump structure.

7. The method of claim 1 further comprising singulating the mold wafer into individual mold modules.

8. The method of claim 1 , wherein the silicon handle layer, the stop layer, and the device layer are formed from a silicon-on-insulator (SOI) structure, wherein the silicon handle layer is a silicon substrate of the SOI structure, the stop layer is a buried oxide (BOX) layer of the SOI structure, and the device layer is formed from a silicon epitaxy layer of the SOI structure.

9. The method of claim 1 , wherein the device layer provides one of a group consisting of a microelectromechanical systems (MEMS) device, an integrated passive device, and an active device.

10. The method of claim 1 , wherein the precursor wafer further comprises a passivation layer formed over the device layer, wherein a portion of each of the plurality of I/O contacts is exposed through the passivation layer and each of the plurality of first bump structures protrudes from a top surface of the passivation layer and is coupled to the exposed portion of a corresponding I/O contact through the passivation layer.

11. The method of claim 10 further comprising patterning the passivation layer to form a plurality of discrete passivation pads before applying the first mold compound over the device layer, wherein:
each of plurality of discrete passivation pads is aligned over a corresponding I/O contact;
a portion of each of the plurality of I/O contacts is exposed through a corresponding discrete passivation pad;
each of the plurality of first bump structures protrudes from a top surface of the corresponding discrete passivation pad and is coupled to the exposed portion of a corresponding I/O contact through the corresponding discrete passivation pad; and
each of plurality of discrete passivation pads is encapsulated by the first mold compound.

12. The method of claim 10 wherein the passivation layer is formed of benzocyclobutene (BCB) or polyimide.

13. The method of claim 1 further comprising forming at least one window component over the device layer before applying the first mold compound over the device layer, wherein:
the at least one window component has a height greater than each of the plurality of first bump structures and is not in contact with the plurality of first bump structures; and
the at least one window component is encapsulated by the first mold compound.

14. The method of claim 13 wherein a portion of the at least one window component is exposed after thinning down the first mold compound.

15. The method of claim 14 further comprising removing the at least one window component to expose a portion of the top surface of the device layer.

16. The method of claim 13 wherein the at least one window component is transparent.

17. The method of claim 1 , wherein the precursor wafer further comprises a redistribution structure formed over the device layer, wherein:
each of the plurality of first bump structures protrudes from a top surface of the redistribution structure;
the redistribution structure includes redistribution interconnects that connect the plurality of I/O contacts to certain ones of the plurality of first bump structures; and
the first mold compound resides over the redistribution structure.

18. The method of claim 1 , wherein the first mold compound is formed from a same material as the second mold compound.

19. The method of claim 18 , wherein:
the first mold compound and the second mold compound have a thermal conductivity greater than 1 W/m·K; and
the first mold compound and the second mold compound have a dielectric constant less than 7.

20. The method of claim 1 , wherein the first mold compound and the second mold compound are formed from different materials.

21. The method of claim 1 , wherein the first mold compound is transparent.

22. The method of claim 1 , wherein the stop layer is formed of at least one of silicon oxide or silicon nitride.

Assignees

• Qorvo Us Inc

Inventors

• Costa Julio C
• Hatcher Jr Merrill Albert
• Wright Peter V
• Chadwick Jon

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P50/287

  by chemical means · CPC title