Selective film forming method and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10490443-B2
Application number	US-201816144311-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 28, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A method of selectively forming a thin film on a substrate to be processed in which a conductive film and an insulating film are exposed to a surface of the substrate includes: selectively forming a first Ru film only on a first surface, which is an exposed surface of the conductive film and formed of one of Ru, RuO2, Pt, Pd, CuO, and CuO2, using an Ru(EtCp)2 gas and an O2 gas; and selectively forming a first SiO2-containing insulating film only on a second surface, which is an exposed surface of the insulating film has OH groups, by performing one or more times a process of supplying a TMA gas to the substrate to adsorb TMA only to the second surface and a process of forming an SiO2 film only on a surface of the adsorbed TMA using a silanol group-containing silicon raw material and an oxidizing agent.

First claim

What is claimed is:

1. A selective film forming method of selectively forming a thin film on a substrate to be processed in which a conductive film and an insulating film are exposed to a surface of the substrate,
wherein a first surface which is an exposed surface of the conductive film is formed of one of Ru, RuO 2 , Pt, Pd, CuO, and CuO 2 , and a second surface which is an exposed surface of the insulating film has OH groups, and
wherein the method comprises:
selectively forming a first Ru film having a first film thickness only on the first surface using an Ru(EtCp) 2 gas and an O 2 gas; and
selectively forming a first SiO 2 -containing insulating film having a second film thickness only on the second surface by performing one or more times a process of supplying a TMA gas to the substrate to adsorb TMA only to the second surface and a process of forming an SiO 2 film only on a surface of the adsorbed TMA using a silanol group-containing silicon raw material and an oxidizing agent.

2. The selective film forming method of claim 1 , further comprising:
selectively forming a second Ru film only on a surface of the first Ru film using the Ru(EtCp) 2 gas and the O 2 gas; and
selectively forming a second SiO 2 -containing insulating film having a third film thickness only on a surface of the first SiO 2 -containing insulating film by performing one or more times a process of adsorbing TMA only to the surface of the first SiO 2 -containing insulating film and a process of forming an SiO 2 film only on a surface of the adsorbed TMA using the silanol group-containing silicon raw material and the oxidizing agent,
wherein the process of selectively forming the second Ru film and the process of selectively forming the second SiO 2 -containing insulating film are performed once or alternately performed multiple times.

3. The selective film forming method of claim 1 , wherein the silanol group-containing silicon raw material is tris(tert-pentoxy)silanol (TPSOL) or tris(tert-butoxy)silanol (TBSOL).

4. A method of manufacturing a semiconductor device, comprising:
preparing a substrate to be processed having an interlayer insulating film formed on a surface of the substrate, the interlayer insulating film having a recess of a predetermined pattern formed on a surface of the interlayer insulating film;
burying a conductive film formed of one of Ru, RuO 2 , Pt, Pd, Cu, CuO, and CuO 2 in the recess;
etching the conductive film so that a surface of the conductive film in the recess is at the same height as a surface of the interlayer insulating film or at a predetermined depth position from the surface of the interlayer insulating film;
when the conductive film is formed of Cu, oxidizing the surface of the conductive film into CuO or CuO 2 ;
selectively forming a first Ru film having a first film thickness only on a first surface, which is an exposed surface of the conductive film and is formed of one of Ru, RuO 2 , Pt, Pd, CuO, and CuO 2 , using an Ru(EtCp) 2 gas and an O 2 gas; and
selectively forming a first SiO 2 -containing insulating film having a second film thickness only on a second surface, which is an exposed surface of the interlayer insulating film having OH groups, by performing one or more times a process of supplying TMA to the substrate to adsorb TMA only to the second surface and a process of forming an SiO 2 film only on a surface of the adsorbed TMA using a silanol group-containing silicon raw material and an oxidizing agent.

5. The method of claim 4 , further comprising:
selectively forming a second Ru film only on a surface of the first Ru film using the Ru(EtCp) 2 gas and the O 2 gas; and
selectively forming a second SiO 2 -containing insulating film having a third film thickness only on a surface of the first SiO 2 -containing insulating film by performing one or more times a process of adsorbing TMA only to the surface of the first SiO 2 -containing insulating film and a process of forming an SiO 2 film only on the surface of the adsorbed TMA using the silanol group-containing silicon raw material and the oxidizing agent,
wherein the process of selectively forming the second Ru film and the process of selectively forming the second SiO 2 -containing insulating film are performed once or alternately performed multiple times.

6. The method of claim 4 , further comprising:
before the process of burying the conductive film, forming a barrier film on the surface of the interlayer insulating film,
wherein the process of etching the conductive film includes removing the barrier film formed on portions other than the recess.

7. The method of claim 6 , wherein the barrier film is selected from TiN, TaN, TiSiCN, TaSiCN, MnO, NiO, and HfO.

8. The method of claim 4 , wherein the silanol group-containing silicon raw material is tris(tert-pentoxy)silanol (TPSOL) or tris(tert-butoxy)silanol (TBSOL).

Assignees

• Tokyo Electron Ltd

Inventors

• Kawano Yumiko
• Azumo Shuji
• Murakami Hiroki
• Aita Michitaka
• Ishizaka Tadahiro
• Akiyama Koji
• Kashiwagi Yusaku
• Nakabayashi Hajime

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title