TFT and manufacturing method thereof, array substrate and manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-10483296-B2
Application number	US-201515300362-A
Country	US
Kind code	B2
Filing date	Oct 19, 2015
Priority date	Jun 8, 2015
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are disclosed. The manufacturing method of a TFT includes: forming an active layer, a gate electrode, a source electrode and a drain electrode respectively electrically connected with the active layer, and a gate insulating layer disposed between the gate electrode and the active layer, so that the gate electrode, the source electrode and the drain electrode are formed in the same patterning process. The method can reduce the number of masks used in the manufacturing process of the TFT or an array substrate, reduce the technology process, improve the productivity, and reduce the production cost.

First claim

What is claimed is:

1. An array substrate, comprising a thin-film transistor (TFT) disposed on a base substrate, wherein the TFT includes:
an active layer;
a gate electrode, a source electrode, and a drain electrode respectively electrically connected with the active layer; and
a gate insulating layer disposed between the gate electrode and the active layer, wherein the gate electrode, the source electrode, and the drain electrode are formed by a same film layer, and wherein materials of the gate electrode, the source electrode, and the drain electrode are the same,
wherein the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed in a same pattering process, and the same patterning process is performed using a single mask.

2. The array substrate according to claim 1 , further comprising a plurality of first signal lines extended along a first direction and a plurality of second signal lines extended along a second direction and insulated from the first signal lines,
wherein each first signal line includes a plurality of spaced linear portions and connecting portions for connecting adjacent linear portions; the connecting portions and the linear portions are arranged in different layers; the linear portions and the second signal lines are arranged in a same layer; and
the first signal lines are gate lines and the second signal lines are data lines; or the first signal lines are data lines and the second signal lines are gate lines.

3. The array substrate according to claim 1 , wherein the gate insulating layer is disposed on the active layer; and the gate electrode, the source electrode, and the drain electrode are disposed on the gate insulating layer.

4. The array substrate according to claim 3 , wherein the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion, which are spaced from each other;
the first insulating portion is disposed between the source electrode and the active layer;
the second insulating portion is disposed between the gate electrode and the active layer; and
the third insulating portion is disposed between the drain electrode and the active layer.

5. The array substrate according to claim 4 , wherein a first opening is disposed between the first insulating portion and the second insulating portion; a second opening is disposed between the second insulating portion and the third insulating portion; and
a width of the active layer is equal to a sum of widths of the first insulating portion, the first opening, the second insulating portion, the second opening, and the third insulating portion, in a direction parallel to the base substrate.

6. The array substrate according to claim 4 , wherein
the source electrode is electrically connected with the active layer through a first conductive structure, wherein the first conductive structure makes contact with an upper surface of the source electrode and a part of an upper surface of the active layer; and
the drain electrode is electrically connected with the active layer through a second conductive structure, wherein the second conductive structure makes contact with an upper surface of the drain electrode and another part of the upper surface of the active layer.

7. The array substrate according to claim 6 , further comprising: a pixel electrode electrically connected with the drain electrode and a common electrode arranged in different layers from the pixel electrode, wherein
the first conductive structure, the second conductive structure, and the pixel electrode are formed in a same one process and made from a same material, or the first conductive structure, the second conductive structure, and the common electrode are formed in a same one process and made from a same material.

8. The array substrate according to claim 1 , wherein the gate insulating layer is disposed on the gate electrode, the source electrode, and the drain electrode; and the active layer is disposed on the gate insulating layer.

9. The array substrate according to claim 1 , wherein the source electrode and the drain electrode make contact with the active layer.

10. The array substrate according to claim 9 , wherein the gate insulating layer is provided with via holes respectively corresponding to the source electrode and the drain electrode; and the source electrode and the drain electrode respectively make contact with the active layer through the via holes; or
the source electrode and the drain electrode are lapped and connected to the active layer.

11. A display device, comprising the array substrate according to claim 1 .

12. A method for manufacturing a thin film transistor (TFT), comprising:
forming an active layer, and a gate electrode, a source electrode, and a drain electrode respectively electrically connected with the active layer, and forming a gate insulating layer disposed between the gate electrode and the active layer, wherein
the gate electrode, the source electrode, and the drain electrode are formed by a same film layer, and wherein materials of the gate electrode, the source electrode, and the drain electrode are the same,
wherein the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed in a same patterning process, and the same patterning process is performed using a single mask.

13. The method according to claim 12 , wherein the active layer, the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed in the same patterning process by a half-tone mask.

14. The method according to claim 13 , wherein
the active layer, the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed by a first patterning process;
a surface of the active layer not covered by the gate insulating layer is subjected to ion implantation or plasma treatment; and
a first conductive structure for electrically connecting the source electrode and the active layer, and a second conductive structure for electrically connecting the drain electrode and the active layer, are formed by a second patterning process.

15. The method according to claim 12 , wherein
the active layer is formed by a first patterning process;
the gate insulating layer, and the gate electrode, the source electrode, and the drain electrode, disposed on the gate insulating layer, are formed on the active layer by a second patterning process;
at least part of a surface of the active layer not covered by the gate insulating layer is subjected to ion implantation or plasma treatment; and
a first conductive structure for electrically connecting the source electrode and the active layer, and a second conductive structure for connecting the drain electrode and the active layer, are formed by a third patterning process.

16. A method for manufacturing an array substrate, comprising: forming a thin film transistor (TFT) on a base substrate, wherein the TFT is manufactured by the method according to claim 12 .

17. The method according to claim 16 , further comprising:
forming a pixel electrode electrically connected with the drain electrode, and forming a common electrode arranged in a different layer from the pixel electrode, wherein
the active layer, the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed by a first patterning process;
a surface of the active layer not covered by the gate insulating layer is subjected to ion implantation or plasma treatment; and
the pixel

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yang Wei
• Liu Xiang

Classifications

• H10P30/202

  characterised by the semiconductor materials · CPC title

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title

• G02F2201/121

  common or background · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title