MLC based magnetic random access memory used in CNN based digital IC for AI

Patent metadata

Field	Value
Publication number	US-10481815-B2
Application number	US-201916403678-A
Country	US
Kind code	B2
Filing date	May 6, 2019
Priority date	Apr 3, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.

First claim

What is claimed is:

1. A digital integrated circuit for artificial intelligence comprising:
a semi-conductor substrate embedded in a single semi-conductor chip, the semi-conductor substrate containing a plurality of cellular neural networks (CNN) processing units, each CNN processing unit comprising:
CNN logic circuits; and
an embedded memory subsystem operatively coupling to the CNN logic circuits;
the embedded memory subsystem further comprising:
an array of first magnetic random access memory cells configured for storing a set of weights; and
an array of second magnetic random access memory cells configured for storing the input signals that require higher endurance of balanced data read and write operations than the array of the first magnetic random access memory cells, each of the first and second magnetic random access memory cells containing at least two vertically stacked magnetic tunnel junction (MTJ) elements.

2. The digital integrated circuit of claim 1 , further comprises at least one input/output data bus operatively coupling to the plurality of the CNN processing units via the memory subsystem and a controller for controlling operations of the plurality of CNN processing units.

3. The digital integrated circuit of claim 2 , wherein said each of the first and second magnetic random access memory cells comprises a multi-level cell spin transfer torque magnetic random access memory (MLC STT-RAM) cell.

4. The digital integrated circuit of claim 2 , wherein said each of the first and second magnetic random access memory cells comprises a multi-level cell orthogonal spin transfer magnetic random access memory (MLC OST-MRAM) cell.

5. The digital integrated circuit of claim 2 , wherein the semi-conductor substrate comprises a silicon substrate.

6. A digital integrated circuit for artificial intelligence comprising:
a semi-conductor substrate embedded in a single semi-conductor chip, the semi-conductor substrate containing a plurality of cellular neural networks (CNN) processing units, each CNN processing unit comprising:
CNN logic circuits; and
an embedded memory subsystem operatively coupling to the CNN logic circuits; the embedded memory subsystem further comprising:
an array of first magnetic random access memory cells configured for storing a set of one-time-programming weights; and
an array of second magnetic random access memory cells configured for storing the input signals that require higher endurance of balanced data read and write operations than the array of the first magnetic random access memory cells, each of the first and second magnetic random access memory cells containing at least two vertically stacked magnetic tunnel junction (MTJ) elements.

7. The digital integrated circuit of claim 6 , further comprises at least one input/output data bus operatively coupling to the plurality of the CNN processing units via the memory subsystem and a controller for controlling operations of the plurality of CNN processing units.

8. The digital integrated circuit of claim 7 , wherein the semi-conductor substrate comprises a silicon substrate.

9. The digital integrated circuit of claim 7 , wherein each MTJ element contains an oxide barrier layer.

10. The digital integrated circuit of claim 9 , wherein the set of one-time-programming weights is created by breaking down the oxide barrier layer of the MTJ element by using at least one of following techniques:
(a) applying an electric voltage larger than a voltage range for normal read/write operations;
(b) applying a longer duty cycle of electric current than normal read/write time;
(c) configuring different sizes for the MTJ elements, whereby a smaller size allows easier break-down of the respective oxide barrier layers; and
(d) setting a different gate length of a transistor, whereby a larger transistor allows larger electric current to break down the respective oxide barrier layers.

11. The digital integrated circuit of claim 9 , wherein said each of the first and second magnetic random access memory cells comprises a multi-level cell spin transfer torque magnetic random access memory (MLC STT-RAM) cell.

12. The digital integrated circuit of claim 9 , wherein said each of the first and second magnetic random access memory cells comprises a multi-level cell orthogonal spin transfer magnetic random access memory (MLC OST-MRAM) cell.

Assignees

• Gyrfalcon Tech Inc

Inventors

• Torng Chyu-Jiuh
• Yang Lin
• Dong Qi

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G06N3/063

  using electronic means · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title