SM4 acceleration processors, methods, systems, and instructions

Patent metadata

Field	Value
Publication number	US-10476667-B2
Application number	US-201816147650-A
Country	US
Kind code	B2
Filing date	Sep 29, 2018
Priority date	Jul 22, 2014
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

First claim

What is claimed is:

1. A system on a chip (SoC) comprising:
an integrated memory controller; and
a processor core coupled to the integrated memory controller, the processor core comprising:
a data cache;
a data TLB coupled to the data cache;
a branch prediction unit;
an instruction cache;
an instruction translation lookaside buffer (TLB) coupled to the instruction cache;
an instruction fetch unit to fetch instructions, including an instruction;
a level 2 (L2) cache coupled to the data cache, and coupled to the instruction cache;
a plurality of registers to store single instruction, multiple data (SIMD) data, including a first register, and a second register, the first register to store a first source data that includes four round keys corresponding to four prior key expansion rounds of an SM4 cryptographic algorithm, the second register to store a second source data that includes four key generation constants;
a decode unit to decode the instruction, the instruction having a first field to specify the first register, a second field to specify the second register, and a third field to specify a destination register of the plurality of registers; and
an execution unit coupled to the decode unit, and coupled to the plurality of registers, the execution unit, in response to the decode of the instruction, to generate and store a result in the destination register, the result to include four round keys corresponding to four sequential key expansion rounds of the SM4 cryptographic algorithm that sequentially follow the four prior key expansion rounds, wherein the execution unit is to generate each of the four round keys to be consistent with an evaluation of a key expansion linear substitution function with a value for the corresponding key expansion round, which is equal to the value logically XOR'd with the value rotated left by thirteen bits logically XOR'd with the value rotated left by twenty-three bits.

2. The SoC of claim 1 , wherein the second source data is 128-bits and is to include:
a first key generation constant for a fourth most recent of the four prior key expansion rounds in bits [31:0];
a second key generation constant for a third most recent of the four prior key expansion rounds in bits [63:32];
a third key generation constant for a second most recent of the four prior key expansion rounds in bits [95:64]; and
a fourth key generation constant for a most recent of the four prior key expansion rounds in bits [127:96].

3. The SoC of claim 1 , wherein the result is 128-bits and is to include:
a fifth round key for a fourth most recent of the four sequential key expansion rounds in bits [31:0];
a sixth round key for a third most recent of the four sequential key expansion rounds in bits [63:32];
a seventh round key for a second most recent of the four sequential key expansion rounds in bits [95:64]; and
an eighth round key for a most recent of the four sequential key expansion rounds in bits [127:96].

4. The SoC of claim 1 , wherein the execution unit, in response to the decode of the instruction, is to generate each of the four round keys by performing a mixer substitution for the corresponding sequential key expansion round, the mixer substitution including a linear substitution on a result of a non-linear substitution.

5. The SoC of claim 1 , wherein the processor core is a reduced instruction set computing (RISC) processor core.

6. The SoC of claim 1 , wherein the first source data is to have a first round key in bits [31:0], a second round key in bits [63:32], a third round key in bits [95:64], and a fourth round key in bits [127:96], wherein the second source data is to have a first key generation constant in bits [31:0], a second key generation constant in bits [63:32], a third key generation constant in bits [95:64], and a fourth key generation constant in bits [127:96], and wherein the result is to include a fifth round key in bits [31:0] that is equal to the first round key logically exclusive OR'd (XOR'd) with a first output of a function evaluated with a first input, the first input equal to the second round key logically XOR'd with the third round key logically XOR'd with the fourth round key logically XOR'd with the first key generation constant, the first output equal to a first value, which is equal to a substitution box applied to the first input, logically XOR'd with the first value rotated left by thirteen bits logically XOR'd with the first value rotated left by twenty-three bits.

7. The SoC of claim 6 , wherein the result is further to include:
a sixth round key in bits [63:32] that is equal to the second round key logically XOR'd with a second output of the function evaluated with a second input, the second input equal to the third round key logically XOR'd with the fourth round key logically XOR'd with the fifth round key logically XOR'd with the second key generation constant, the second output equal to a second value, which is equal to a substitution box applied to the second input, logically XOR'd with the second value rotated left by thirteen bits logically XOR'd with the second value rotated left by twenty-three bits;
a seventh round key in bits [95:64] that is equal to the third round key logically XOR'd with a third output of the function evaluated with a third input, the third input equal to the fourth round key logically XOR'd with the fifth round key logically XOR'd with the sixth round key logically XOR'd with the third key generation constant, the third output equal to a third value, which is equal to a substitution box applied to the third input, logically XOR'd with the third value rotated left by thirteen bits logically XOR'd with the third value rotated left by twenty-three bits; and
an eighth round key in bits [127:96] that is equal to the fourth round key logically XOR'd with a fourth output of the function evaluated with a fourth input, the fourth input equal to the fifth round key logically XOR'd with the sixth round key logically XOR'd with the seventh round key logically XOR'd with the fourth key generation constant, the fourth output equal to a fourth value, which is equal to a substitution box applied to the fourth input, logically XOR'd with the fourth value rotated left by thirteen bits logically XOR'd with the fourth value rotated left by twenty-three bits.

8. The SoC of claim 1 , further comprising a graphics processing unit coupled to the processor core.

9. The SoC of claim 1 , further comprising an image processor coupled to the processor core.

10. The SoC of claim 1 , further comprising an audio processor coupled to the processor core.

11. The SoC of claim 1 , further comprising a coprocessor coupled to the processor core.

12. The SoC of claim 1 , further comprising a communication processor coupled to the processor core.

13. The SoC of claim 1 , further comprising a network processor coupled to the processor core.

14. The SoC of claim 1 , further comprising a display unit coupled to the processor core, the display unit to couple an external display.

15. The SoC of claim 1 , further comprising an interconnect coupled to the processor core and the integrated memory controller.

16. The SoC of claim 15 , wherein the interconnect comprises a ring interconnect.

17. The SoC of claim 1 , further comprising a direct memory access (DMA) unit coupled to the processor core.

18. A system on a chip (SoC) comprising:
an integrated memory controller; and
a processor core coupled to the integrated memory controller, the processor core comprising:
a plurality of registers to store single

Assignees

• Intel Corp

Inventors

• Gueron Shay
• Krasnov Vlad

Classifications

• H04L9/0625

  with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L2209/80

  Wireless · CPC title

• H04L9/0631

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title

• G06F9/30156

  Special purpose encoding of instructions, e.g. Gray coding · CPC title