Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Patent metadata

Field	Value
Publication number	US-9467279-B2
Application number	US-201414498633-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Sep 26, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

First claim

What is claimed is:

1. A processor comprising:
a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) SM4 operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and
one or more execution units, responsive to the decoded first instruction, to:
perform one or more SM4-round exchange of a portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set if a first indicator of said one or more substitution function indicators indicates a first substitution function;
perform one or more SM4 key generation using said portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set if a second indicator of said one or more substitution function indicators indicates a second substitution function; and
store a result of the first instruction in a SIMD destination register.

2. The processor of claim 1 , wherein the first instruction specifies said SIMD destination register as a destination operand.

3. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold four 32-bit elements as the first source data operand set.

4. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold eight 32-bit elements as the first source data operand set.

5. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold sixteen 32-bit elements as the first source data operand set.

6. The processor of claim 1 , wherein the first instruction specifies said one or more substitution function indicators in the first instruction mnemonic.

7. The processor of claim 1 , wherein said one or more execution units, responsive to the decoded first instruction, performs four SM4-round exchanges of, or four SM4 key generation using said portion of the first source data operand set.

8. The processor of claim 1 , wherein said first substitution function is the SM4 mixer-substitution function, T.

9. The processor of claim 8 , wherein said second substitution function is the SM4 key expansion substitution function, T′.

10. The processor of claim 1 , wherein the first instruction specifies said one or more substitution function indicators as an immediate byte operand.

11. The processor of claim 10 , wherein the first instruction specifies said one or more substitution function indicators by setting one bit in the immediate byte operand for each corresponding lane of four 32-bit elements in the first source data operand set.

12. A machine-readable medium to record functional descriptive material having stored thereon one or more executable instructions including a first instruction, which if executed on behalf of a thread of a machine causes the machine to:
access a first source data operand set of elements, a second source data operand set of elements, and one or more substitution function indicators;
perform a first one or more SM4-round exchange of a portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that indicates a first substitution function;
perform a first one or more SM4 key generation using said portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set in response to a second indicator of said one or more substitution function indicators that indicates a second substitution function; and
store a set of result elements of the one or more SM4-round exchange and the one or more SM4 key generation in a SIMD register.

13. The machine-readable medium of claim 12 , said one or more executable instructions also including a second instruction, which if executed on behalf of the thread of said machine further causes the machine to:
access the set of result elements of the one or more SM4-round exchange and the one or more SM4 key generation in the SIMD register, a third source data operand set of elements, and another one or more substitution function indicators;
perform a second one or more SM4-round exchange of a portion of the set of result elements with a corresponding second one or more keys from the third source data operand set in response to a third indicator of said another one or more substitution function indicators that indicates the first substitution function;
perform a second one or more SM4 key generation using said portion of the set of result elements with a corresponding second one or more constants from the third source data operand set in response to a fourth indicator of said another one or more substitution function indicators that indicates the second substitution function; and
store another set of result elements of the second one or more SM4-round exchange and second one or more SM4 key generation in the SIMD register.

14. The machine-readable medium of claim 13 , wherein said first substitution function is the SM4 mixer-substitution function, T.

15. The machine-readable medium of claim 14 , wherein said second substitution function is the SM4 key expansion substitution function, T′.

16. The machine-readable medium of claim 15 , said one or more executable instructions, if executed on behalf of the thread of said machine further causes the machine to:
store, in a second SIMD register, the third source data operand set of elements; and
repeat execution of said second instruction on behalf of the thread of said machine.

17. The machine-readable medium of claim 16 , wherein said one or more executable instructions, if executed on behalf of the thread of said machine cause said storing in the second SIMD register and repeating of the execution of said second instruction until at least thirty-two SM4-round exchanges and SM4 key generations are performed on behalf of the thread of said machine.

18. The machine-readable medium of claim 17 , wherein said one or more executable instructions, if executed on behalf of the thread of said machine cause said repeating of the execution of said second instruction not more than fifteen times after execution of the first instruction to complete the thirty-two SM4-round exchanges and SM4 key generations on behalf of the thread of said machine.

19. The machine-readable medium of claim 18 , wherein said one or more executable instructions, if executed on behalf of the thread of said machine cause said repeating of the execution of said second instruction only seven times after execution of the first instruction to complete the thirty-two SM4-round exchanges and SM4 key generations on behalf of the thread of said machine.

20. A method comprising:
decoding a first instruction for a Single Instruction Multiple Data (SIMD) SM4 round slice operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and
responsive to the first instruction,
accessing the first source data operand set,
accessing the second source data operand set,
performing a first plurality of SM4-round exchanges on a first portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that in

Assignees

• Intel Corp

Inventors

• Wolrich Gilbert M
• Gulley Sean M
• Gopal Vinodh
• Yap Kirk S
• Feghali Wajdi K

Classifications

• H04L2209/24

  Key scheduling, i.e. generating round keys or sub-keys for block encryption · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L9/0618 Primary

  Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title