On-the-fly key generation for encryption and decryption

Patent metadata

Field	Value
Publication number	US-9544133-B2
Application number	US-64745909-A
Country	US
Kind code	B2
Filing date	Dec 26, 2009
Priority date	Dec 26, 2009
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.

First claim

The invention claimed is:

1. An apparatus for generating new encrypt or decrypt round keys per machine cycle, the apparatus comprising:
a first logic circuit to generate a second cipher key, in a second cycle, based on a first cipher key, wherein the first cipher key is to be generated by the same first logic circuit in a first cycle that immediately precedes the second cycle, and wherein the first logic circuit is to comprise a plurality of substitution boxes to perform substitute byte operations on portions of the first cipher key to generate corresponding portions of the second cipher key;
a second logic circuit to encrypt or decrypt content data based on the second cipher key, wherein the first logic circuit is to generate the second cipher key without storing data in a shared memory and wherein the shared memory is accessible by more than a producer and a consumer;
logic circuitry to rotate a portion of the first cipher key, wherein a substitution box is to perform a substitute byte operation on the rotated portion of the first cipher key to generate a corresponding portion of the second cipher key; and
a logic block to conditionally perform an inverse mix columns operation to generate the second cipher key during a decrypt mode if the second cipher key is not a first round decrypt key or a last round decrypt key.

2. The apparatus of claim 1 , wherein the first logic circuit is to generate the second cipher key in a single cycle.

3. The apparatus of claim 1 , wherein the first logic circuit is to generate the second cipher key in accordance with Advanced Encryption Standard (AES).

4. The apparatus of claim 1 , wherein the first logic circuit is to generate the second cipher key for one or more of mapped or native composite Galois Field encryption or decryption.

5. The apparatus of claim 1 , wherein the first logic circuit is capable to generate the second cipher key in accordance with Advanced Encryption Standard (AES), AES-128, AES-192, and AES-256 modes.

6. The apparatus of claim 1 , wherein the initial key is user supplied key.

7. The apparatus of claim 1 , further comprising a processor that is to comprise the first logic circuit.

8. The apparatus of claim 7 , wherein the processor is to comprise a plurality of processor cores and wherein at least one of the plurality of processor cores is to comprise the first logic circuit.

9. A system for generating new encrypt or decrypt round keys per machine cycle, the system comprising:
a memory to store content data;
a first logic circuit to generate a second cipher key, in a second cycle, based on a first cipher key, wherein the first cipher key is to be generated by the same first logic circuit in a first cycle that immediately follows the second cycle; and wherein the first logic circuit is to comprise a plurality of substitution boxes to perform substitute byte operations on portions of the first cipher key to generate corresponding portions of the second cipher key;
a second logic circuit to encrypt or decrypt the content data based on the second cipher key, wherein the first logic circuit is to generate the second cipher key without storing data in a shared memory accessible by more than a producer and a consumer;
logic circuitry to rotate a portion of the first cipher key, wherein a substitution box is to perform a substitute byte operation on the rotated portion of the first cipher key to generate a corresponding portion of the second cipher key; and
a logic block to conditionally perform an inverse mix columns operation to generate the second cipher key during a decrypt mode if the second cipher key is not a first round decrypt key or a last round decrypt key.

10. The system of claim 9 , further comprising an audio device coupled to the first logic circuit.

Assignees

• Mathew Sanu K
• Sheikh Farhana
• Krishnamurthy Ram K
• Kounavis Michael E
• Gueron Shay
• Intel Corp

Inventors

• Mathew Sanu K
• Sheikh Farhana
• Krishnamurthy Ram K
• Kounavis Michael E
• Gueron Shay

Classifications

• H04L9/3073

  involving pairings, e.g. identity based encryption [IBE], bilinear mappings or bilinear pairings, e.g. Weil or Tate pairing · CPC title

• H04L9/0631 Primary

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title

• H04L2209/24

  Key scheduling, i.e. generating round keys or sub-keys for block encryption · CPC title