Self-aligned nanowire formation using double patterning

Patent metadata

Field	Value
Publication number	US-9633907-B2
Application number	US-201414289167-A
Country	US
Kind code	B2
Filing date	May 28, 2014
Priority date	May 28, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

First claim

What is claimed is:

1. A method comprising:
forming a pattern-reservation layer over a semiconductor substrate, wherein the semiconductor substrate comprises a major surface;
performing a first self-aligned multi-patterning process to etch the pattern-reservation layer, wherein remaining portions of the pattern-reservation layer comprise pattern-reservation strips having first lengthwise directions extending in a first direction that is parallel to the major surface of the semiconductor substrate;
performing a second self-aligned multi-patterning process to etch the pattern-reservation strips formed by the first self-aligned multi-patterning process, wherein the first self-aligned multi-patterning process and the second self-aligned multi-patterning process comprise a first etching step and a second etching step, respectively, with the first etching step and the second etching step being separate etching steps, wherein etching masks used in the second self-aligned multi-patterning process have second lengthwise directions extending in a second direction parallel to the major surface of the semiconductor substrate, wherein remaining portions of the pattern-reservation layer comprise patterned features; and
using the patterned features as an additional etching mask to form semiconductor nanowires by etching the semiconductor substrate.

2. The method of claim 1 , wherein each of the first self-aligned multi-patterning process and the second self-aligned multi-patterning process comprises:
forming a mandrel layer;
etching the mandrel layer to form mandrel strips, wherein the mandrel strips of the first self-aligned multi-patterning process have lengthwise directions in the first direction;
forming a spacer layer over the mandrel layer;
removing horizontal portions of the spacer layer, wherein vertical portions of the mandrel layer form spacers;
removing the mandrel strips; and
etching the pattern-reservation layer using the mandrel strips as an etching mask.

3. The method of claim 2 further comprising forming an oxide layer over the pattern-reservation layer, wherein during the first self-aligned multi-patterning process, the oxide layer is patterned.

4. The method of claim 3 , wherein after the first self-aligned multi-patterning process, the oxide layer comprises remaining oxide strips over the pattern-reservation strips, and wherein the method further comprises filling spaces between the remaining oxide strips with a filling material, with the filling material being patterned in the second self-aligned multi-patterning process.

5. The method of claim 1 , wherein the first direction is perpendicular to the second direction.

6. The method of claim 1 , wherein the first direction is neither perpendicular to nor parallel to the second direction.

7. The method of claim 1 further comprising, after the first self-aligned multi-patterning process and the second self-aligned multi-patterning process, forming a photo resist over the semiconductor substrate, wherein in the etching the semiconductor substrate, a pattern of the photo resist is transferred into the semiconductor substrate.

8. A method comprising:
forming a pattern-reservation layer over a semiconductor substrate;
etching the pattern-reservation layer using a first self-aligned multi-patterning process to form pattern-reservation strips;
forming a filling material to fill spaces between the pattern-reservation strips;
etching the pattern-reservation strips using a second self-aligned multi-patterning process, wherein remaining portions of the pattern-reservation strips form patterned features, wherein each of the first self-aligned multi-patterning process and the second self-aligned multi-patterning process comprises:
forming mandrel strips, wherein the mandrel strips of the first self-aligned multi-patterning process have a first lengthwise direction different from a second lengthwise direction of the mandrel strips of the second self-aligned multi-patterning process;
forming spacers on sidewalls of the mandrel strips; and
removing the mandrel strips, wherein the mandrel strips are used as an etching mask to etch the pattern-reservation layer in the first self-aligned multi-patterning process and the second self-aligned multi-patterning process; and

using the patterned features as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

9. The method of claim 8 , wherein the forming the mandrel strips comprises:
forming an amorphous silicon layer; and
patterning the amorphous silicon layer.

10. The method of claim 8 further comprising:
forming a pad dielectric layer over the semiconductor substrate;
forming a hard mask over the pad dielectric layer, with the hard mask being under the pattern-reservation layer; and
patterning the hard mask and the pad dielectric layer using the patterned features as the etching mask.

11. The method of claim 8 , wherein the first lengthwise direction is perpendicular to the second lengthwise direction.

12. The method of claim 8 , wherein after the first self-aligned multi-patterning process, the spaces are empty, and the forming the filling material to fill the spaces comprises Flowable Chemical Vapor Deposition (FCVD) or spin-on coating.

13. The method of claim 8 further comprising forming a transistor, wherein a middle portion of one of the semiconductor nanowires forms a channel region of the transistor, and wherein an upper portion and a lower portion of the one of the semiconductor nanowires form source and drain regions of the transistor.

14. A method comprising:
forming a pattern-reservation layer over a semiconductor substrate;
forming first mandrel strips over the pattern-reservation layer;
forming first spacers on sidewalls of the first mandrel strips;
removing the first mandrel strips;
using the first spacers as etching masks to etch the pattern-reservation layer, with remaining portions of the pattern-reservation layer forming pattern-reservation strips;
forming second mandrel strips over the pattern-reservation strips;
forming second spacers on sidewalls of the second mandrel strips;
removing the second mandrel strips; and
using the second spacers as etching masks to etch the pattern-reservation strips, with remaining portions of the pattern-reservation strips forming first nanowires.

15. The method of claim 14 further comprising using the first nanowires as additional etching masks to etching an underlying layer.

16. The method of claim 15 , wherein the etching the underlying layer comprises etching the semiconductor substrate to form semiconductor nanowires.

17. The method of claim 16 further comprising forming transistors, with portions of the semiconductor nanowires being channels of the transistors.

18. The method of claim 14 further comprising forming an oxide layer over the pattern-reservation layer, wherein when the pattern-reservation layer is etched and when the pattern-reservation strips are etched, the oxide layer is etched as oxide nanowires.

19. The method of claim 14 , wherein the first mandrel strips extend in a first lengthwise direction un-parallel to a second lengthwise direction of the second mandrel strips, wherein the first lengthwise direction and the second lengthwise direction are parallel to a major top surface of the semiconductor substrate.

20. The method of claim 14 further comprising, between the pattern-reservation layer is etched and the pattern-reservation strips are etched, filling spaces between the patter

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fu Ching-Feng
• Chen De-Fang
• Yen Yu-Chan
• Lee Chia-Ying
• Lee Chun-Hung
• Lin Huan-Just

Classifications

• H10P50/696

  Process specially adapted to improve the resolution of the mask · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/43

  Layouts of interconnections · CPC title