Semiconductor structure

Patent metadata

Field	Value
Publication number	US-10475755-B2
Application number	US-201816173450-A
Country	US
Kind code	B2
Filing date	Oct 29, 2018
Priority date	Oct 30, 2015
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A method of manufacturing a semiconductor structure includes providing a transceiver, forming a molding to surround the transceiver, forming a plurality of recesses extending through the molding, disposing a conductive material into the plurality of recesses to form a plurality of vias, disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver, and forming a redistribution layer (RDL) over the insulating layer, wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a charger configured to convert a charging power from AC to DC;
a transceiver configured to transmit or receive a signal in a predetermined electromagnetic frequency;
a molding surrounding the transceiver and the charger;
a plurality of vias extending through the molding;
an antenna configured to transmit or receive the signal to/from an ambient environment; and
a dielectric layer covering the antenna,
wherein the antenna comprises an elongated portion extending over the molding and a via portion electrically connected to the transceiver.

2. The semiconductor structure of claim 1 , wherein the antenna is configured to receive a signal in the predetermined electromagnetic frequency from a transmitter, and the plurality of vias is configured to receive the charging power from the transmitter.

3. The semiconductor structure of claim 1 , wherein each of the plurality of vias is a through integrated circuit via (TIV) extending through the molding and inductively coupled with the antenna.

4. The semiconductor structure of claim 1 , wherein the antenna has a resonance frequency of about 2.4 GHz.

5. The semiconductor structure of claim 1 , wherein the antenna is a Bluetooth antenna.

6. The semiconductor structure of claim 1 , wherein the molding has a thickness of about 100 μm and 200 μm.

7. The semiconductor structure of claim 1 , further comprising a pillar electrically connecting the via portion of the antenna and the transceiver.

8. The semiconductor structure of claim 7 , further comprising an insulating layer disposed over the molding, the plurality of vias and the pillar.

9. The semiconductor structure of claim 8 , wherein the via portion of the antenna extends through the insulating layer to contact the pillar.

10. The semiconductor structure of claim 7 , wherein the pillar and the antenna comprise a same material.

11. A semiconductor structure comprising:
a charger;
a transceiver;
a molding surrounding the transceiver and the charger;
a plurality of vias extending through the molding;
an insulating layer disposed over the molding, the charger, the transceiver and the plurality of vias; and
a redistribution layer (RDL) disposed over the insulating layer, wherein the RDL comprises:
an antenna disposed over and electrically connected to the transceiver;
a first interconnect structure electrically connected to the plurality of vias; and
a second interconnect structure electrically connected to the charger,

wherein a portion of the antenna extends through the insulating layer to electrically connect to the transceiver.

12. The semiconductor structure of claim 11 , further comprising a first pillar disposed between the antenna and the transceiver and surrounded by the molding, wherein the first pillar electrically connects the portion of the antenna and the transceiver.

13. The semiconductor structure of claim 11 , further comprising a plurality of second pillars disposed between the charger and the second interconnect structure and surrounded by the molding, wherein the plurality of second pillars electrically connects the second interconnect structure and the charger.

14. The semiconductor structure of claim 11 , wherein the RDL further comprises a third interconnect structure disposed over the transceiver and electrically connected to the transceiver.

15. The semiconductor structure of claim 14 , further comprising a third pillar disposed between the third interconnect structure and the transceiver and surrounded by the molding, wherein the third pillar electrically connects the third interconnect structure and the transceiver.

16. A semiconductor structure comprising:
a charger;
a transceiver;
a resonator;
a molding surrounding the transceiver, the charger and the resonator;
a plurality of vias extending through the molding;
an insulating layer disposed over the molding, the charger, the transceiver, the resonator and the plurality of vias; and
a redistribution layer (RDL) disposed over the insulating layer, wherein the RDL comprises:
an antenna disposed over and electrically connected to the transceiver;
a first interconnect structure electrically connected to the plurality of vias; and
a second interconnect structure electrically connected to the charger,

wherein a portion of the antenna extends through the insulating layer to electrically connect to the transceiver.

17. The semiconductor structure of claim 16 , wherein each of the plurality of vias is a through integrated circuit via (TIV) extending through the molding and inductively coupled with the antenna.

18. The semiconductor structure of claim 16 , wherein the resonator is electrically connected with the charger and at least one of the plurality of vias.

19. The semiconductor structure of claim 16 , further comprising a pillar electrically connecting the via portion of the antenna and the transceiver, wherein the pillar and the antenna comprise a same material.

20. The semiconductor structure of claim 19 , wherein the via portion of the antenna extends through the insulating layer to contact the pillar.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Vincent
• Kuo Hung-Yi
• Wang Chuei-Tang
• Tsai Hao-Yi
• Yu Chen-Hua
• Chen Wei-Ting
• Tseng Ming Hung
• Lin Yen-Liang

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title