Semiconductor device having a metal adhesion and barrier structure and a method of forming such a semiconductor device

Patent metadata

Field	Value
Publication number	US-10475743-B2
Application number	US-201715458366-A
Country	US
Kind code	B2
Filing date	Mar 14, 2017
Priority date	Mar 15, 2016
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a metal structure electrically connected to a semiconductor body; and
a metal adhesion and barrier structure between the metal structure and the semiconductor body,
wherein the metal adhesion and barrier structure comprises:
a first layer comprising titanium and tungsten;
a second layer comprising titanium, tungsten, and nitrogen on the first layer comprising titanium and tungsten;
a third layer comprising tungsten on the second layer comprising titanium, tungsten, and nitrogen; and
a fourth layer comprising titanium and tungsten on the third layer comprising tungsten.

2. The semiconductor device of claim 1 , wherein the first layer comprising titanium and tungsten is a TiW layer having a thickness in a range of 30 nm to 600 nm.

3. The semiconductor device of claim 1 , wherein a thickness of the second layer comprising titanium, tungsten, and nitrogen is in a range of 30 nm to 600 nm.

4. The semiconductor device of claim 1 , further comprising a metal adhesion and barrier substructure between the semiconductor body and the first layer comprising titanium and tungsten, the metal adhesion and barrier substructure being in contact with the semiconductor body.

5. The semiconductor device of claim 4 , wherein the metal adhesion and barrier substructure is made of one or a combination of TiW, TiN, Ti/TiN, and TaN/Ta.

6. The semiconductor device of claim 5 , wherein a thickness of the metal adhesion and barrier substructure is in a range of 30 nm to 600 nm.

7. The semiconductor device of claim 1 , wherein the atomic percent of nitrogen in the second layer comprising titanium, tungsten, and nitrogen is in a range of 1% to 50%.

8. A semiconductor device, comprising:
a metal structure electrically connected to a semiconductor body; and
a metal adhesion and barrier structure between the metal structure and the semiconductor body,
wherein the metal adhesion and barrier structure comprises:
a first layer comprising Al and Cu;
a second layer comprising Ti; and
a third layer comprising TiN,
wherein the first layer comprising Al and Cu is in contact with the semiconductor body.

9. The semiconductor device of claim 8 , wherein the first layer comprising Al and Cu further comprises Si.

10. The semiconductor device of claim 8 , wherein a thickness of the third layer comprising TiN is in a range of 5 nm and 150 nm.

11. The semiconductor device of claim 8 , wherein a thickness of the second layer comprising Ti is in a range of 1 nm and 150 nm.

12. The semiconductor device of claim 8 , wherein the metal structure comprises a copper layer in direct contact with the metal adhesion and barrier structure, a thickness of the copper layer being greater than 4 μm.

13. The semiconductor device of claim 12 , further comprising at least one more metal layer on the copper layer.

14. A method of manufacturing a semiconductor device, the method comprising:
forming a metal adhesion and barrier structure on a semiconductor body;
forming a metal structure on the metal adhesion and barrier structure, wherein formation of the metal adhesion and barrier layer comprises:
forming a first layer comprising titanium and tungsten;
forming a second layer comprising titanium, tungsten, and nitrogen on the first layer comprising titanium and tungsten; and
forming a third layer comprising tungsten on the second layer comprising titanium, tungsten, and nitrogen,
wherein the method further comprises:
forming a fourth layer of the metal adhesion and barrier layer on the third layer comprising tungsten, the fourth layer comprising titanium and tungsten; and/or
forming a metal adhesion and barrier substructure between the semiconductor body and the first layer comprising titanium and tungsten, the metal adhesion and barrier substructure being in contact with the semiconductor body.

15. The method of claim 14 , wherein forming the second layer comprising titanium, tungsten, and nitrogen comprises:
forming a layer comprising titanium and tungsten; and
nitriding the layer comprising titanium and tungsten.

16. The method of claim 14 , wherein the second layer comprising titanium, tungsten, and nitrogen is formed by a sputter process.

17. The method of claim 14 , further comprising performing surface cleaning processes prior to formation of one or both of the first layer comprising titanium and tungsten and the second layer comprising titanium, tungsten, and nitrogen.

18. The method of claim 14 , wherein one or both of the first layer comprising titanium and tungsten and the second layer comprising titanium, tungsten, and nitrogen is formed by chemical vapor deposition.

19. The method of claim 14 , wherein an uppermost part of the metal adhesion and barrier structure and a lowermost part of the metal structure are formed in a same processing chamber without interruption of vacuum conditions.

20. A semiconductor device, comprising:
a metal structure electrically connected to a semiconductor body; and
a metal adhesion and barrier structure between the metal structure and the semiconductor body, the metal adhesion and barrier structure comprising a first layer comprising titanium and tungsten, a second layer comprising titanium, tungsten, and nitrogen on the first layer comprising titanium and tungsten, and a third layer comprising tungsten on the second layer comprising titanium, tungsten, and nitrogen; and
a metal adhesion and barrier substructure between the semiconductor body and the first layer comprising titanium and tungsten, the metal adhesion and barrier substructure being in contact with the semiconductor body.

21. The semiconductor device of claim 20 , wherein the metal adhesion and barrier substructure is made of one or a combination of TiW, TiN, Ti/TiN, and TaN/Ta.

22. The semiconductor device of claim 21 , wherein a thickness of the metal adhesion and barrier substructure is in a range of 30 nm to 600 nm.

23. A semiconductor device, comprising:
a metal structure electrically connected to a semiconductor body; and
a metal adhesion and barrier structure between the metal structure and the semiconductor body,
wherein the metal adhesion and barrier structure comprises:
a TiW layer;
a TiWN layer on the TiW layer; and
a W layer on the TiWN layer.

24. A method of manufacturing a semiconductor device, the method comprising:
forming a metal adhesion and barrier structure on a semiconductor body; and
forming a metal structure on the metal adhesion and barrier structure,
wherein forming the metal adhesion and barrier layer comprises:
forming a TiW layer;
forming a TiWN layer on the TiW layer; and
forming a W layer on the TiWN layer.

25. The method of claim 24 , wherein forming the TiWN layer on the TiW layer comprises:
forming a layer comprising titanium and tungsten on the TiW layer; and
nitriding the layer comprising titanium and tungsten.

Assignees

• Infineon Technologies Ag

Inventors

• Hille Frank
• Joshi Ravi Keshav
• Fugger Michael
• Humbel Oliver
• Laska Thomas
• Mueller Matthias
• Roth Roman
• Schaeffer Carsten
• Schulze Hans-Joachim
• Schulze Holger
• Steinbrenner Juergen
• Umbach Frank

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/052

  by treatments not introducing additional elements therein · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title