Method for forming semiconductor device structure having conductive structure with twin boundaries

Patent metadata

Field	Value
Publication number	US-10475742-B2
Application number	US-201816205997-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Aug 21, 2015
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A method of forming a semiconductor device structure includes: forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and wherein the forming the first conductive structure includes manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density and such that the first conductive structure has a resistance which is substantially the same as the second conductive structure.

First claim

What is claimed is:

1. A method for forming a semiconductor device structure, the method comprising:
forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and
wherein the forming the first conductive structure includes:
manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that:
the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density; and
the first conductive structure has an ohmic resistance which is substantially the same as the second conductive structure.

2. The method of claim 1 , wherein the forming a first conductive structure further includes:
performing a pulse current type of electrodeposition process.

3. The method of claim 2 , wherein:
a spacing between a first twin boundary and a second twin boundary is a twin-lamella width; and
the forming a first conductive structure further includes:
manipulating process conditions so as to promote formation of twin-lamella widths within a range.

4. The method of claim 1 , wherein the forming the first conductive structure further includes:
forming a diffusion barrier layer; and
forming a conductive material over the diffusion barrier layer, wherein a lattice mismatch ratio between a lattice constant of the diffusion barrier layer and a lattice constant of the conductive material is in a range from about 0.1% to about 6%.

5. The method of claim 4 , further comprising:
forming a glue layer between the diffusion barrier layer and the conductive material, wherein a lattice mismatch ratio between a lattice constant of the glue layer and the lattice constant of the conductive material is in a range from about 0.1% to about 6%.

6. The method of claim 1 , further comprising:
forming a via-trench structure over the first conductive structure, wherein the via-trench structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1 .

7. The method of claim 1 , wherein:
the manipulating process conditions achieves a density of the twin boundaries which is in a range from about 25 μm −1 to about 250 μm −1 .

8. A method for forming a semiconductor device structure, the method comprising:
forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and
wherein:
a spacing between a first twin boundary and a second twin boundary is a twin-lamella width; and
the forming the first conductive structure includes:
manipulating process conditions so as to promote formation of a first range of twin-lamella widths such that:
the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted second range of twin-lamella widths ;

a measure of central tendency of the first range is smaller than the measure of central tendency of the second range; and
the first conductive structure has an ohmic resistance which is substantially the same as the second conductive structure.

9. The method of claim 8 , wherein:
the measure of central tendency is average twin-lamella width.

10. The method of claim 9 , wherein:
the average twin-lamella width of the first range is from about 4 nm to about 40 nm.

11. The method of claim 8 , wherein the forming a conductive structure further includes:
performing a pulse current type of electrodeposition process.

12. The method of claim 8 , wherein the forming the first conductive structure further includes:
forming a diffusion barrier layer; and
forming a conductive material formed over the diffusion barrier layer, wherein a lattice mismatch ratio between a lattice constant of the diffusion barrier layer and a lattice constant of the conductive material is in a range from about 0.1% to about 6%.

13. The method of claim 12 , further comprising:
forming a glue layer between the diffusion barrier layer and the conductive material, wherein a lattice mismatch ratio between a lattice constant of the glue layer and the lattice constant of the conductive material is in a range from about 0.1% to about 6%.

14. The method of claim 8 , further comprising:
forming a via-trench structure over the first conductive structure, wherein the via-trench structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1 .

15. The method of claim 8 , wherein:
the manipulating process conditions achieves a density of the twin boundaries which is in a range from about 25 μm −1 to about 250 μm −1 .

16. The method of claim 3 , wherein:
the range is a range of values of average twin-lamella width; and
the range is from about 4 nm to about 40 nm.

17. A method for forming a semiconductor device structure, the method comprising:
forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and
forming a via-trench structure over the first conductive structure, the via-trench structure including twin boundaries; and
wherein the forming the first conductive structure includes:
manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that:
the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density; and
the first conductive structure has an ohmic resistance which is substantially the same as the second conductive structure.

18. The method of claim 17 , wherein:
a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1.

19. The method of claim 17 , wherein:
a spacing between a first twin boundary and a second twin boundary is a twin-lamella width; and
the manipulating process conditions includes:
promoting formation of twin-lamella widths having a measure of central tendency within a range.

20. The method of claim 19 , wherein:
the measure of central tendency is average twin-lamella width.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jian-Hong
• Chiu Chwei-Ching
• Lee Yung-Huei
• Liao Chien-Neng
• Chueh Yu-Lun
• Chan Tsung-Cheng
• Huang Chun-Lung

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title