Self aligned buried power rail

US10475692B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10475692-B2
Application numberUS-201715481826-A
CountryUS
Kind codeB2
Filing dateApr 7, 2017
Priority dateApr 7, 2017
Publication dateNov 12, 2019
Grant dateNov 12, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

First claim

Opening claim text (preview).

What is claimed: 1. A method, comprising: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure, wherein: the forming of the at least one fin structure of the first dimension comprises a first spacer transfer process which forms a first spacer that defines the at least one fin structure of the first dimension; the forming of the at least one fin structure of the second dimension comprises a second spacer transfer process which forms a second spacer that defines the at least one fin structure of the second dimension; and the second spacer is wider than the first spacer. 2. The method of claim 1 , wherein the first dimension is narrower than the second dimension. 3. The method of claim 1 , wherein the filling of the trench with the conductive metal includes lining the trench with a conductive barrier material and filling remaining portions of the trench with metal fill material, where the metal trench is self-aligned within the original fin grating. 4. The method of claim 3 , further comprising recessing of the conductive barrier material and the metal fill material, and depositing a capping material over the recessed conductive barrier material and the metal fill material. 5. The method of claim 3 , wherein the removing of the at least a portion of the at least one fin structure of the second dimension includes completely removing of the at least one fin structure of the second dimension. 6. The method of claim 3 , wherein the removing of the at least a portion of the at least one fin structure of the second dimension includes partially removing of the at least one fin structure of the second dimension. 7. The method of claim 3 , wherein the trench is lined with an insulator material under the conductive barrier material. 8. The method of claim 1 , wherein: the second spacer is positioned above the first spacer. 9. The method of claim 8 , wherein the second spacer overlaps with edges of the first spacer. 10. The method of claim 1 , wherein the filling of the trench with the conductive metal is an electroless metal fill process, performed over a barrier liner material. 11. The method of claim 1 , wherein the trench is isolated from the at least one fin structure of the first dimension by gap fill material. 12. A method comprising: forming a first spacer of a first dimension over a substrate material; forming a second spacer of a second dimension, wider than the first dimension and above the first spacer; transferring the first dimension of the first spacer into the substrate to form a narrow fin structure; transferring the second dimension of the second spacer into the substrate to form a wide fin structure, wherein the narrow fin structure is narrower than the wide fin structure; removing at least part of the wide fin structure to form a trench, which is isolated from the narrow fin structure; forming a buried power rail by filling the trench with conductive material; and forming a contact to the buried power rail. 13. The method of claim 12 , further comprising removing the second spacer and the first spacer after forming of the wide fin structure and the narrow fin structure. 14. The method of claim 13 , wherein the filling of the trench with the conductive material comprises: lining the trench with a conductive barrier material and filling remaining portions of the trench with metal fill material; and recessing of the conductive barrier material and the metal fill material. 15. The method of claim 14 , further comprising depositing a capping material over the recessed conductive barrier material and the metal fill material. 16. The method of claim 12 , wherein the removing at least part of the wide fin structure includes partially removing of the wide fin structure. 17. The method of claim 12 , wherein the trench is lined with an insulator material under the conductive material. 18. The method of claim 12 , wherein the filling of the trench with the conductive metal is an electroless metal fill process, performed over a barrier liner material.

Assignees

Inventors

Classifications

  • Power or ground buses · CPC title

  • Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

  • H10W20/021Primary

    of interconnections within wafers or substrates · CPC title

  • H01L21/743Primary

    Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US10475692B2 cover?
The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the seco…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/021. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 12 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).