Stabilizing the startup behavior of ring oscillators

Patent metadata

Field	Value
Publication number	US-10469059-B1
Application number	US-201715853152-A
Country	US
Kind code	B1
Filing date	Dec 22, 2017
Priority date	Dec 22, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A system for providing security in a computer system is provided. The system includes a ring oscillator including a plurality of logic gates connected in a ring configuration. The system also includes logic circuits to start the ring oscillator by a ring-enable signal and a clock signal provided to a clock input of at least one controlled logic gate of the plurality of logic gates. The clock signal controls the at least one controlled logic gate and thereby synchronizes the ring oscillator to the clock signal. The clock signal is provided to the clock input for a predetermined warm-up duration, and thereafter, the logic circuits restart and operate the ring oscillator without the clock signal.

First claim

What is claimed is:

1. A method of operating a ring oscillator, the ring oscillator comprising a plurality of logic gates connected in a ring configuration in which an output of each of the plurality of logic gates is used as an input for a next one of the plurality of logic gates, the output of the last of the plurality of logic gates being fed back to and used as an input for a first of the plurality of logic gates, the method comprising:
starting the ring oscillator by a ring-enable signal and a clock signal provided to a clock input of at least one controlled logic gate of the plurality of logic gates in the ring configuration, the at least one controlled logic gate receiving the clock signal to control the at least one controlled logic gate and thereby synchronize the ring oscillator to the clock signal, the clock signal being provided to the clock input for a predetermined warm-up duration, wherein each of the plurality of logic gates causes a gate delay in signal propagation within the ring oscillator, and starting the ring oscillator includes starting the ring oscillator by the ring-enable signal and the clock signal that includes a periodic train of pulses having a pulse-width that is the gate delay or an integer multiple of the gate delay; and thereafter,
restarting and operating the ring oscillator without the clock signal.

2. The method of claim 1 , wherein the plurality of logic gates includes an odd number of inverting logic gates connected in the ring configuration, and
wherein the at least one controlled logic gate has a synchronizing input that is the clock input to which the clock signal is provided.

3. The method of claim 1 , wherein the at least one controlled logic gate includes a differential buffer gate having a non-inverted input and an inverted input, and at least an inverted output, the non-inverted input being connected to an output of a previous one of the plurality of logic gates in the ring configuration, the inverted input being the clock input, the inverted output being connected to an input for a next one of the plurality of logic gates in the ring configuration, and
wherein starting the ring oscillator includes starting the ring oscillator by the ring-enable signal and the clock signal provided to the inverted input of the differential buffer gate.

4. The method of claim 1 , wherein the at least one controlled logic gate includes a tri-state inverter having an input connected to an output of a previous one of the plurality of logic gates in the ring configuration, an inverted output connected to an input of a next one of the inverting logic gates in the ring configuration, and a gate enable input that is the clock input, and
wherein starting the ring oscillator includes starting the ring oscillator by the ring-enable signal and the clock signal provided to the enable input of the tri-state inverter.

5. The method of claim 1 , wherein the at least one controlled logic gate includes a gated D-latch having a data input and an enable input, and at least an inverted output, the data input being connected to an output of a previous one of the plurality of logic gates in the ring configuration, the enable input being the clock input, and the inverted output being connected to an input for a next one of the plurality of logic gates in the ring configuration, and
wherein starting the ring oscillator includes starting the ring oscillator by the ring-enable signal and the clock signal provided to the enable input of the gated D-latch.

6. The method of claim 1 , wherein the at least one controlled logic gate includes a 2:1 multiplexer connected between consecutive logic gates of the plurality of logic gates in the ring configuration, the 2:1 multiplexer having a first input and a second input, a selector input and an output, the first input being connected to an output of an earlier one of the consecutive logic gates in the ring configuration, the selector input being the clock input, and the output being both connected to an input for a later one of the consecutive logic gates in the ring configuration, and fed back and connected to the second input of the 2:1 multiplexer, and
wherein starting the ring oscillator includes starting the ring oscillator by the ring-enable signal and the clock signal provided to the selector input of the 2:1 multiplexer.

7. The method of claim 1 , wherein the clock signal has a clock frequency, and restarting and operating the ring oscillator includes restarting and operating the ring oscillator at a frequency that is the clock frequency or a multiple of the clock frequency.

8. The method of claim 1 , wherein the at least one controlled logic gate is multiple controlled logic gates each of which includes a respective clock input that receives the clock signal to control the multiple controlled logic gates and thereby synchronize the ring oscillator to the clock signal.

9. A system for providing security in a computer system, the system comprising a ring oscillator, the ring oscillator comprising a plurality of logic gates connected in a ring configuration in which an output of each of the plurality of logic gates is used as an input for a next one of the plurality of logic gates, the output of the last of the plurality of logic gates being fed back to and used as an input for a first of the plurality of logic gates, the system also comprising one or more logic circuits configured to at least:
start the ring oscillator by a ring-enable signal and a clock signal provided to a clock input of at least one controlled logic gate of the plurality of logic gates in the ring configuration, the at least one controlled logic gate receiving the clock signal to control the at least one controlled logic gate and thereby synchronize the ring oscillator to the clock signal, the clock signal being provided to the clock input for a predetermined warm-up duration, wherein each of the plurality of logic gates causes a gate delay in signal propagation within the ring oscillator, and the one or more logic circuits being configured to start the ring oscillator includes being configured to start the ring oscillator by the ring-enable signal and the clock signal that includes a periodic train of pulses having a pulse-width that is the gate delay or an integer multiple of the gate delay; and thereafter,
restart and operate the ring oscillator without the clock signal.

10. The system of claim 9 , wherein the plurality of logic gates includes an odd number of inverting logic gates connected in the ring configuration, and wherein the at least one controlled logic gate has a synchronizing input that is the clock input to which the clock signal is provided.

11. The system of claim 9 , wherein the at least one controlled logic gate includes a differential buffer gate having a non-inverted input and an inverted input, and at least an inverted output, the non-inverted input being connected to an output of a previous one of the plurality of logic gates in the ring configuration, the inverted input being the clock input, the inverted output being connected to an input for a next one of the plurality of logic gates in the ring configuration, and
wherein the one or more logic circuits being configured to start the ring oscillator includes being configured to start the ring oscillator by the ring-enable signal and with the clock signal provided to the inverted input of the differential buffer gate.

12. The system of claim 9 , wherein the at least one controlled logic gate includes a tri-state inverter having an input connected to an output of a previous one of the plurality of logic gates in the ring configuration, an inverted output connected to an input of a next on

Assignees

• Boeing Co

Inventors

• Hars Laszlo

Classifications

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/1733

  Controllable logic circuits (H03K19/177 takes precedence) · CPC title

• H03K2005/00234

  using circuits having two logic levels · CPC title

• H03K3/0315 Primary

  Ring oscillators · CPC title