True random number generator

Patent metadata

Field	Value
Publication number	US-9531354-B1
Application number	US-201514745275-A
Country	US
Kind code	B1
Filing date	Jun 19, 2015
Priority date	Jun 19, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A random number generator is disclosed. In some embodiments, the random number generator comprises two cross-coupled inverter chains, wherein each inverter chain comprises an odd number of gates including an input NAND gate; wherein when a clock signal input into the NAND gate of both inverter chains switches from low to high, the inverter chains start toggling until a noise induced phase difference automatically collapses the toggling after a random number of cycles; and wherein a random number generated by the random number generator is based on the random number of cycles.

First claim

What is claimed is:

1. A random number generator, comprising:
inverter chains including a first inverter chain and
a second inverter chain cross-coupled to the first inverter chain; and
at least a capacitor connected between outputs of the inverter chains,
wherein each of the inverter chains comprises an odd number of gates including an input NAND gate; wherein when a clock signal input into the NAND gate of the inverter chains switches from low to high, the inverter chains start toggling until a noise induced phase difference automatically collapses the toggling after a random number of cycles; and wherein a random number generated by the random number generator is based on the random number of cycles.

2. The random number generator of claim 1 , wherein the random number generator comprises a true random number generator.

3. The random number generator of claim 1 , wherein the first and the second inverter chains comprise two cross-coupled ring oscillators.

4. The random number generator of claim 1 , wherein the output of each inverter chain is input into the other inverter chain.

5. The random number generator of claim 1 , wherein each inverter chain comprises an even number of inverters.

6. The random number generator of claim 1 , wherein each inverter chain comprises two inverters.

7. The random number generator of claim 1 , wherein both inverter chains are symmetric.

8. The random number generator of claim 1 , wherein the random number generator is reset when the clock signal input into the NAND gate of both inverter chains goes low.

9. The random number generator of claim 1 , further comprising symmetric capacitors connected between the outputs of the inverter chains.

10. The random number generator of claim 1 , wherein the random number comprises a single random bit comprising an output value of the first inverter chain or the second inverter chain when toggling collapses.

11. The random number generator of claim 1 , further comprising a counter configured to count n bits of the random number of cycles to generate n parallel random bits, wherein n is an integer greater than zero.

12. The random number generator of claim 11 , wherein the counter is configured to count less than a minimum number of cycles the inverter chains are expected to oscillate.

13. The random number generator of claim 1 , wherein the cross-coupled inverter chains comprise one of a plurality of cross-coupled inverter chains and wherein the random number is generated by combining outputs of the plurality of cross-coupled inverter chains.

14. A method, comprising:
configuring inverter chains including a first inverter chain and a second inverter chain;
cross-coupling the second inverter chain with the first inverter chain; and
connecting at lease a capacitor between outputs of the inverter chains,
wherein each of the inverter chains comprises an odd number of gates including an input NAND gate; wherein when a clock signal input into the NAND gate of the inverter chains switches from low to high, the inverter chains start toggling until a noise induced phase difference automatically collapses the toggling after a random number of cycles; and wherein a random number is generated based on the random number of cycles.

15. The method of claim 14 , wherein the output of each inverter chain is input into the other inverter chain.

16. The method of claim 14 , wherein each inverter chain comprises an even number of inverters.

17. The method of claim 14 , wherein the random number comprises a single random bit comprising an output value of the first inverter chain or the second inverter chain when toggling collapses.

18. The method of claim 14 , further comprising configuring a counter to count n bits of the random number of cycles to generate n parallel random bits, wherein n is an integer greater than zero.

Assignees

• Sk Hynix Memory Solutions Inc

Inventors

• Sim Yukeun

Classifications

• H03K3/84 Primary

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K3/0315

  Ring oscillators · CPC title